R7FA2L1AB2DFM datasheet(34/114 Pages) RENESAS

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Table 2.18

Operation frequency in middle-speed mode

Conditions: VCC = AVCC0 = 1.6 to 5.5 V

Parameter

Symbol

Min

Typ

Max*4

Unit

Operation

frequency

System clock (ICLK)*1*2

1.8 to 5.5 V

0.032768 —

MHz

1.6 to 1.8 V

0.032768 —

Peripheral module clock (PCLKB)

1.8 to 5.5 V

—

1.6 to 1.8 V

—

Peripheral module clock (PCLKD)*3

1.8 to 5.5 V

—

1.6 to 1.8 V

—

Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory. When using ICLK for programming or

erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as

1.5 MHz cannot be set.

Note 2. The frequency accuracy of ICLK must be ± 1.0% while programming or erasing the flash memory. Confirm the frequency accuracy

of the clock source.

Note 3. The lower-limit frequency of PCLKD is 1 MHz when the ADC12 is in use.

Note 4. The maximum value of operation frequency does not include internal oscillator errors. For details on the range for guaranteed

operation, see Table 2.21.

Table 2.19

Operation frequency in low-speed mode

Conditions: VCC = AVCC0 = 1.6 to 5.5 V

Parameter

Symbol

Min

Typ

Max*4

Unit

Operation

frequency

System clock (ICLK)*1*2

1.6 to 5.5 V

0.032768 —

MHz

Peripheral module clock (PCLKB)

1.6 to 5.5 V

—

Peripheral module clock (PCLKD)*3

1.6 to 5.5 V

—

Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory.

Note 2. The frequency accuracy of ICLK must be ± 1.0% while programming or erasing the flash memory. Confirm the frequency accuracy

of the clock source.

Note 3. The lower-limit frequency of PCLKD is 1 MHz when the ADC12 is in use.

Note 4. The maximum value of operation frequency does not include internal oscillator errors. For details on the range for guaranteed

operation, see Table 2.21.

Table 2.20

Operation frequency in Subosc-speed mode

Conditions: VCC = AVCC0 = 1.6 to 5.5 V

Parameter

Symbol

Min

Typ

Max

Unit

Operation

frequency

System clock (ICLK)*1

1.6 to 5.5 V

27.8528

32.768

37.6832

kHz

Peripheral module clock (PCLKB)

1.6 to 5.5 V

—

37.6832

Peripheral module clock (PCLKD)*2

1.6 to 5.5 V

—

37.6832

Note 1. Programming and erasing the flash memory is not possible.

Note 2. The ADC12 cannot be used.

2.3.2

Clock Timing

Table 2.21

Clock timing (1 of 2)

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

EXTAL external clock input cycle time

tXcyc

—

Figure 2.3

EXTAL external clock input high pulse width

tXH

—

EXTAL external clock input low pulse width

tXL

—

EXTAL external clock rising time

tXr

—

EXTAL external clock falling time

tXf

—

EXTAL external clock input wait time*1

tEXWT

0.3

—

µs

—

EXTAL external clock input frequency

fEXTAL

—

MHz

1.8 ≤ VCC ≤ 5.5

RA2L1 Datasheet

2. Electrical Characteristics

R01DS0385EJ0160 Rev.1.60

Oct 14, 2025

Page 34 of 114

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