H8SLASH300H datasheet(103/552 Pages) RENESAS

103 / 552 page

Section 4 Clock Pulse Generators

Rev. 3.00 May 15, 2007 Page 71 of 518

REJ09B0152-0300

4.4

Prescalers

This LSI is equipped with two on-chip prescalers (prescaler S and prescaler W), which have

different input clocks.

Prescaler S is a 13-bit counter using the system clock (

φ) as its input clock. Its prescaled outputs

provide internal clock signals for on-chip peripheral modules. Prescaler W is an 8-bit counter

using

W/4, which is 1/4th of the watch clock φW, as its input clock. Its prescaled outputs provide

internal clock signals for on-chip peripheral modules.

4.4.1

Prescaler S

Prescaler S is a 13-bit counter using the system clock (

φ) as its input clock. A divided output is

used as an internal clock of an on-chip peripheral module. Prescaler S is initialized to H'0000 at a

reset, and starts counting up on exit from the reset state. In standby mode, watch mode, subactive

mode, and subsleep mode, prescaler S stops and is initialized to H'0000. The CPU cannot read

from or write to prescaler S.

The output from prescaler S is shared by the on-chip peripheral modules. In active (medium-

speed) mode and sleep (medium-speed) mode, the clock input to prescaler S is determined by the

division ratio designated by the MA1 and MA0 bits in SYSCR1.

4.4.2

Prescaler W

Prescaler W is an 8-bit counter using

W/4, which is 1/4th of the watch clock φW, as its input clock.

A divided output is used as an internal clock of an on-chip peripheral module. Prescaler W is

initialized to H'00 at a reset, and starts counting up on exit from the reset state. In standby mode,

prescaler W is halted. Even when transiting to watch mode, subactive mode, and subsleep mode,

prescaler W continues operation.

H8/300H Datasheet(PDF) 103 Page - Renesas Technology Corp