7643 datasheet(153/424 Pages) RENESAS

153 / 424 page

Rev.2.00

Aug 28, 2006

page 32 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.3 Serial I/O

(2) Serial communication using SPI compatible mode

qExplanation of SPI compatible mode

Setting the SPI mode select bit (bit 0 of SIOCON2) to “1” puts the serial I/O in SPI compatible

mode. The synchronous clock select bit (bit 6 of SIOCON1) determines whether the serial I/O

is an SPI master or slave. When the external clock (SCLK pin input) is selected (“0”), the serial

I/O is in slave mode; when the internal synchronous clock is selected (“1”), the serial I/O is in

master mode.

In SPI compatible mode the SRXD pin functions as a MISO (Master In/Slave Out) pin and the

STXD pin functions as a MOSI (Master Out/Slave In) pin.

In slave mode the transmit data is output from the MISO pin and the receive data is input from

the MISO pin. The SRDY pin functions as the chip-select signal input pin from an external.

In master mode the transmit data is output from the MOSI pin and the receive data is input from

the MISO pin. The SRDY pin functions as the chip-select signal output pin to an external.

qSlave mode operation

In slave mode of SPI compatible mode 4 types of clock polarity and clock phase can be usable

by bits 3 and 4 of serial I/O control register 2.

If the SRDY pin is held “H”, the shift clock is inhibited, the serial I/O counter is set to “7”. If the

SRDY pin is held “L”, then the shift clock will start.

Make sure during transfer to maintain the SRDY input at “L” and not to write data to the serial

I/O counter.

Outline : Serial communication is performed between 7643 group MCUs, using SPI compatible

mode.

Specifications : • Synchronous clock frequency : 187.5 kHz (f(XIN) = 24 MHz )

• Transfer direction : LSB first

Figure 2.3.14 shows a connection diagram; Figure 2.3.15 shows the registers setting for SPI

compatible mode; Figures 2.3.16 and 2.3.17 show a control procedure of SPI compatible mode.

P80/SRDY

P81/SCLK

P82/MISO

P83/MOSI

7643 group

CLK

DATA

Master unit

Slave unit

P80/SRDY

P81/SCLK

P82/MISO

P83/MOSI

7643 group

Fig. 2.3.14 Connection diagram

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