7643 datasheet(156/424 Pages) RENESAS

156 / 424 page

Rev.2.00

Aug 28, 2006

page 35 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.3 Serial I/O

Fig. 2.3.17 Control procedure of SPI compatible mode in master

q x: This bit is not used here. Set it to “0” or “1” arbitrarily.

IREQC (Address : 0416), bit3?

Initialization

SIOCON1

SIOCON2

IREQC

ICONC

(Address : 2B16)

(Address : 2C16)

(Address : 0416), bit3

(Address : 0716), bit3

010111012

000111012

IREQC (Address : 0416), bit3

SIOSHT (Address : 2A16)

Transmi-

ssion data

•Serial I/O interrupt request bit set to “0”

•Serial I/O interrupt disabled

RESET

•Serial I/O set

CLI

•Transmission data write

(Start of transmit 1-byte data)

•Then P80/SRDY pin set to “L”

•Judgment of completion of transmitting 1-byte data

•“L” output from P80/SRDY pin

Master Unit

Read out received data from SIOSHT

(Address : 2A16)

Complete to transmit all data?

•Use any of RAM area as a counter for counting

the number of transmitted bytes

•Judgment of completion of transmitting all data

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