7643 datasheet(154/424 Pages) RENESAS

154 / 424 page

Rev.2.00

Aug 28, 2006

page 33 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.3 Serial I/O

Fig. 2.3.15 Registers setting for SPI compatible mode

SRDY output selected

STXD, SCLK output selected

Serial I/O interrupt : Disabled

ICONC

Interrupt control register C (Address : 0716)

SIOCON1

Serial I/O control register 1 (Address : 2B16)

LSB first

External clock (SCLK pin input)

STXD pin : CMOS output

SPI compatible mode

Serial I/O control register 2 (Address : 2C16)

SIOCON2

SRXD input enabled

qSlave Unit

SCLK starting at “H”

Serial transfer starting afer a half cycle of SCLK

passed at falling edge of SRDY

No SRDY output

STXD, SCLK output selected

Serial I/O interrupt : Disabled

ICONC

Interrupt control register C (Address : 0716)

LSB first

Internal synchronous clock

STXD pin : CMOS output

SPI compatible mode

Serial I/O control register 2 (Address : 2C16)

SIOCON2

SRXD input enabled

SIOCON1

Serial I/O control register 1 (Address : 2B16)

qMaster Unit

SCLK starting at “H”

Serial transfer starting afer a half cycle of SCLK

passed at falling edge of SRDY

Internal synchronous clock :

φ/32

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