7643 datasheet(214/424 Pages) RENESAS

214 / 424 page

Rev.2.00

Aug 28, 2006

page 93 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.5 DMAC

Fig. 2.5.17 Setting of relevant registers (2)

DMA0CL

127

DMA0CH

DMAC channel 0 destination registers Low, High (addresses 4416, 4516)

DMA0DL

6216

DMA0DH

0016

DMA0M1

DMAC channel 0 mode register 2 (address 4116)

DMA0M2

USB interrupt enable register 1 (address 5416)

USBIE1

0 0

USB function interrupt disabled

ICONA

USB endpoint 2 FIFO address (low-order)

USB endpoint 2 FIFO address (high-order)

DMAC channel 0 transfer count registers Low, High (addresses 4616, 4716)

128-byte counts

High-order of transfer counter

DMAC channel 0 mode register 1 (address 4016)

DMAC channel 0 source register increment/decrement disabled

DMAC channel 0 destination register increment/decrement disabled

Channel 0 enabled after count register underflow

Burst transfer mode selected

USB endpoint 2 IN_PKT_RDY signal hardware transfer request source

Software transfer trigger requesting

Reset of channel 0 capture register

Channel 0 enabled

USB endpoint 2 IN interrupt disabled

USB endpoint 2 OUT interrupt disabled

Interrupt control register A (address 0516)

DMAC0 interrupt request

IREQA

Interrupt request register A (address 0216)

DMAC0 interrupt enabled

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