7643 datasheet(213/424 Pages) RENESAS

213 / 424 page

Rev.2.00

Aug 28, 2006

page 92 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.5 DMAC

Fig. 2.5.16 Setting of relevant registers (1)

FSC

φ = f(XIN)/2

Clock control register (address 1F16)

CCR

FSM1

0016

FSM2

FF16

USBC

USBINDEX

IN_MAXP

128

IN_CSR

IN_PKT_RDY bit

AUTO_SET bit

DMAC index and status register (address 3F16)

DMAIS

DMA0SL

XX16

DMA0SH

XX16

000 00

Frequency synthesizer multiply register 1 (address 6D16)

Frequency synthesizer multiply register 2 (address 6E16)

Frequency synthesizer control register (address 6C16)

Frequency synthesizer enabled

f(XIN) selected as frequency synthesizer input

USB control register (address 1316)

“H” current for USB line driver

USB line driver enabled

USB clock enabled

USB block enabled

USB endpoint index register (address 5816)

Endpoint 2

USB endpoint 2 IN max. packet size register (address 5B16)

128 bytes

USB endpoint 2 IN control register (address 5916)

Channel 0 accessible

DMAC channel 0 source registers Low, High (addresses 4216, 4316)

External FIFO address (low-order)

External FIFO address (high-order)

USBFIFOMR

USB endpoint FIFO mode register (address 5F16)

FIFO size selection bit

For endpoint 2

IN 128 bytes,OUT 128 bytes

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