7643 datasheet(209/424 Pages) RENESAS

209 / 424 page

Rev.2.00

Aug 28, 2006

page 88 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.5 DMAC

2.5.4 DMAC arbitration

The DMA transfer request is accepted at a rising

φ. If the bus is not released 1 cycle of φ later

than the transfer request acceptance, the DMAC

will wait for the bus released. When the bus is

released, the DMAC has a right to use the bus

and starts the DMA transfer unless a request of

the right to use the bus having priority over the

DMAC occurs.

Table 2.5.3 shows the priority to use the bus.

Table 2.5.3 Priority to use bus

Priority

1 (Higher)

4 (Lower)

Factor requesting right to use bus

Hold request via HOLD pin

DMAC

CPU data access

CPU instruction access

2.5.5 Transfer time

One-byte transfer of the cycle steal transfer mode requires the time calculated by the following equation:

Time (T) = A + B + C

A: This means the time from the occurrence of DMA transfer source request to sampling it. It needs 1

cycle of

φ at the maximum. The sampling is asynchronously performed.

B: This means the delay time to sample the DMA transfer source request. It needs 1 cycle of

φ at the

maximum.

C: This means the time to transfer data. It needs 2 cycles of

φ.

Figures 2.5.13 to 2.5.15 show the timing chart for DMA transfer.

7643 Datasheet(PDF) 209 Page - Renesas Technology Corp