7643 datasheet(208/424 Pages) RENESAS

208 / 424 page

Rev.2.00

Aug 28, 2006

page 87 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.5 DMAC

Address direction

Source

Destination

Table 2.5.2 Address directions and examples of transfer result (2)

Data arrangement on

transfer source memory

Forward

Backward

Transfer

sequence

Data arrangement on

transfer destination

memory

(Ttransfer result)

Backward

Fixed

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

➀

➁

➂

➃

➄

➅

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6

Data 1 to 6

➀

➁

➂

➃

➄

➅

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Backward

Forward

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

➀

➁

➂

➃

➄

➅

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6

➀

➁

➂

➃

➄

➅

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

(4) Transfer suspension

Writing “0” to the DMAC channel x enable bit (DxCEN) can compulsorily suspend the transfer

being executed. The suspended transfer can be resumed by writing “1” to the DxCEN bit.

When an interrupt request, which is enabled, occurs during any DMA operation, the transfer

operation is suspended and the interrupt process routine is initiated. During the interrupt operation,

the DMAC automatically sets the corresponding DMAC channel x suspend flag to “1”. When the

DMAC transfer suspend control bit (DTSC) is “1”, the transfer is suspended in both burst transfer

and cycle steal transfer modes during an interrupt process; when the DTSC bit is “0”, it is suspended

in only burst transfer mode.

The suspended transfer due to the interrupt can also be resumed during its interrupt process

routine by writing “1” to the DxCEN bit.

Backward

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