7643 datasheet(205/424 Pages) RENESAS

205 / 424 page

Rev.2.00

Aug 28, 2006

page 84 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.5 DMAC

2.5.3 DMAC operation description

The DMAC transfers data using the bus without use of the CPU. The DMAC consists of DMAC0 and

DMAC1, which have the same function each.

There are two transfer modes: Burst transfer mode or Cycle steal transfer mode.

•Burst transfer mode

Once a DMA transfer request is accepted, an entire batch of data is transferred. The right to use bus

is not returned to the CPU until the transfer of all data has been completed.

The DMAC transfers the number of bytes data specified by the transfer count register for each request.

The count register is a 16-bit counter; the maximum number of data is 65,536 bytes per one request.

•Cycle steal mode

The DMAC transfers one byte of data for each request. If one byte transfer has been completed and

then a DMA transfer request is not generated, the right to use bus is returned to the CPU.

Figure 2.5.11 shows the transfer mode overview.

s Burst transfer mode

CPU

DMACx request is accepted.

DMACx (x = 0, 1)

(Transfer of entire batch of data)

CPU

DMAC0

CPU

s Cycle steal transfer mode

CPU

DMAC0

DMAC1

Right to use bus

CPU

Right to use bus

DMAC0 request is accepted.

DMAC0 request

is accepted.

DMAC1 request

is accepted.

(One-byte transfer)

(One-byte transfer)(One-byte transfer)

Fig. 2.5.11 Transfer mode overview

(1) Priority

The DMAC places a higher priority on Channel-0 transfer requests than on Channel-1 transfer

requests.

If a channel-0 transfer request occurs during a channel-1 burst transfer operation, the DMAC

completes the next transfer source and destination read/write operation first, and then starts the

channel-0 transfer operation. As soon as the channel-0 transfer is completed, the DMAC resumes

the channel-1 transfer operation.

(2) Transfer request acceptance

A transfer request is confirmed at every rising of

φ. After that a channel priority and a right to use

the bus is judged.

A software trigger and/or a hardware factor can be selected as a transfer request source. The

DMAC channel x hardware transfer request source bits (DxHR) selects a hardware factor.

Writing “1” to the DMAC channel x software transfer trigger bit (DxSWT) can generate a transfer

request as a software trigger.

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