7643 datasheet(202/424 Pages) RENESAS

202 / 424 page

Rev.2.00

Aug 28, 2006

page 81 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.5 DMAC

Fig. 2.5.6 Structure of DMAC channel x source registers Low, High

DMAC channel x source registers Low, High

b7 b6 b5 b4 b3 b2 b1 b0

DMAC channel x source registers Low, High

(DMAxSL,DMAxSH : addresses 4216, 4316)

Functions

At reset R W

qThis is a 16-bit register with a latch.

qThis register indicates the source address for data transfer.

Notes 1: DMAC channel x source registers low, high of channels 0 and 1 are assigned at

the same addresses. The accessible register depends on channel index bit, bit 7 of

DMAC index and status register.

2: Write data into the lower bytes first, and then the higher bytes.

3: Read the contents from the higher bytes first, and then the lower bytes.

DMAC channel x destination registers Low, High

b7 b6 b5 b4 b3 b2 b1 b0

DMAC channel x destination registers Low, High

(DMAxDL,DMAxDH : addresses 4416, 4516)

Functions

At reset R W

qThis is a 16-bit register with a latch.

qThis register indicates the destination address for data transfer.

Notes 1: DMAC channel x destination registers low, high of channels 0 and 1 are assigned

at the same addresses. The accessible register depends on channel index bit, bit 7

of DMAC index and status register.

2: Write data into the lower bytes first, and then the higher bytes.

3: Read the contents from the higher bytes first, and then the lower bytes.

Fig. 2.5.7 Structure of DMAC channel x destination registers Low, High

7643 Datasheet(PDF) 202 Page - Renesas Technology Corp