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7643 Datasheet(PDF) 199 Page - Renesas Technology Corp |
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7643 Datasheet(HTML) 199 Page - Renesas Technology Corp |
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199 / 424 page  Rev.2.00 Aug 28, 2006 page 78 of 202 7643 Group REJ09B0133-0200 APPLICATION 2.5 DMAC (3) DMAC channel x (x = 0, 1) mode register 2 •DMAC channel x software transfer trigger bit (DxSWT) Writing “1” to the DxSWT bit can generate a transfer request as a software trigger. If all of DMACx hardware transfer request source bits (DxHR) are “0”, the software trigger is only transfer request factor. This bit is fixed to “0” at read. •DMAC channel x transfer initiation source capture register reset bit (DxCRR) Writing “1” to the DxCRR bit can reset the transfer initiation source capture register. The request of the transfer initiation source is latched asynchronously and it is sampled into the transfer initiation source capture register at a rising edge of φ. This bit is fixed to “0” at read. •DMAC channel x enable bit (DxCEN) The DMAC channel x is enabled by setting this bit to “1”. When clearing this to “0”, the DMA transfer is finished. |
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