7643 datasheet(197/424 Pages) RENESAS

197 / 424 page

Rev.2.00

Aug 28, 2006

page 76 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.5 DMAC

2.5.2 Related registers

(1) DMAC index and status register

•DMAC channel x (x = 0, 1) count register underflow flag (DxUF)

When the corresponding transfer count register Low (address 4616) underflows, this DxUF flag

is set to “1”. Writing “0” into this flag clears it.

•DMAC channel x (x = 0, 1) suspend flag (DxSFI)

When an interrupt routine is processed during any DMA operation, the transfer operation is

suspended and the DMAC automatically sets the corresponding DxSFI flag to “1”. As soon as

the CPU completes the interrupt operation, the DMAC clears the DxSFI flag to “0” and resumes

the original operation from the point where it was suspended.

•DMAC transfer suspend control bit (DTSC)

This bit specifies the transfer mode which can be suspended by an interrupt process.

•DMAC register reload disable bit (DRLDD)

If the DRLDD bit is “1”, when the DMAC channel x transfer count register underflows, the DMAC

channel x source registers and destination registers are disabled from being reloaded from their

latches.

•Channel index bit (DCI)

The related registers of channels 1 and 2 are assigned on the same SFR addresses. This DCI

bit specifies the accessible channel.

Fig. 2.5.2 Structure of DMAC index and status register

DMAC index and status register

b7 b6 b5 b4 b3 b2 b1 b0

DMAC index and status register

(DMAIS : address 3F16)

Name

Functions

At reset R W

DMAC channel 0 suspend

flag (D0SFI) (Note 1)

DMAC transfer suspend

control bit (DTSC) (Note 2)

DMAC channel 1 count

0 : No underflow

1 : Underflow generated

0 : Not suspended

1 : Suspended

DMAC channel 1 suspend

flag (D1SFI) (Note 1)

0 : No underflow

1 : Underflow generated

DMAC register reload

disable bit (DRLDD)

(Note 3)

Channel index bit (DCI)

0 : Channel 0 accessible

1 : Channel 1 accessible

Accessed registers: Mode register,

source register, destination register,

transfer count register.

DMAC channel 0 count

Nothing is arranged for this bit.

Fix this bit to “0”.

0 : Not suspended

1 : Suspended

0 :Suspending only burst transfers during

interrupt process

1 : Suspending both burst and cycle steal

transfers during interrupt process

0 :Enabling reload of source and

destination registers of both channels

1 : Disabling reload of source and

destination registers of both channels

Notes 1: Suspended by an interrupt.

2: Transfer suspended during interrupt process

3: This settings affect the source and destination registers of both channels.

✽

✽: “0” can be set by software, but “1” cannot be set.

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