7643 datasheet(194/424 Pages) RENESAS

194 / 424 page

Rev.2.00

Aug 28, 2006

page 73 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.4 UART

2.4.7 Notes on UART

(1) Receive

•When any one of errors occurs, the summing error flag is set to “1” and the UART summing error

interrupt request bit is also set to “1”. If a receive error occurs, the reception does not set the UART

receive buffer full interrupt request bit to “1”.

•If the receive enable bit (REN) is set to “0” (disabled) while a data is being received, the receiving

operation will stop after the data has been received.

•Setting the receive initialization bit (RIN) to “1” resets the UART RTS control register (URTS) to

“8016”. After setting the RIN bit to “1”, set this URTS.

(2) Transmit

•Once the transmission starts, it continues until the last bit has been transmitted even though clearing

the transmit enable bit (TEN) to “0” (disabled) or inputting “H” to the CTS pin. After completion of

the current transmission, the transmission is disabled.

•The transmit complete flag (TCM) is changed from “1” to “0” later than 0.5 to 1.5 clocks of the shift

clock. Accordingly, take it in consideration to transmit data confirming the TCM flag after the data

is written into the transmit buffer register.

(3) Register settings

•If updating a value of UART baud rate generator while the data is being transmitted or received, be

sure to disable the transmission and reception before updating. If the former data remains in the

UART transmit buffer registers 1 and 2 at retransmission, an undefined data might be output.

•The all error flags PER, FER, OER and SER are cleared to “0” when the UART status register is

read, at the hardware reset or initialization by setting the Transmit Initialization Bit. These flags are

also cleared to “0” by execution of bit test instructions such as BBC and BCS.

•The transmit buffer empty flag (TBE) is set to “0” when the low-order byte of transmitted data is

written into the UART transmit buffer register 1. When using 9-bit character length, set the data into

the UART transmit buffer register 2 (high-order byte) first before the UART transmit buffer register

1 (low-order byte).

•The receive buffer full flag (RBF) is set to “0” when the contents of UART receive buffer register 1

is read out. When using 9-bit character length, read the data from the UART receive buffer register

2 (high-order byte) first before the UART receive buffer register 1 (low-order byte).

•If a character bit length is 7 bits, bit 7 of the UART transmit/receive buffer register 1 and bits 0 to

7 of the UART transmit/receive buffer register 2 are ignored at transmitting; they are invalid at

receiving.

If a character bit length is 8 bits, bits 0 to 7 of the UART transmit/receive buffer register 2 are

ignored at transmitting; they are invalid at receiving.

If a character bit length is 9 bits, bits 1 to 7 of the UART transmit/receive buffer register 2 are

ignored at transmitting; they are “0” at receiving.

•The reset cannot affect the contents of baud rate generator.

(4) UART address mode

•When the MSB of the incoming data is “0” in the UART address mode, the receive buffer full flag

(RBF) is set to “1”, but the receive buffer full interrupt request bit is not set to “1”.

•An overrun error cannot be detected after the first data has been received in UART address mode.

•The UART address mode can be used in either an 8-bit or 9-bit character length. 7-bit character

length cannot be used.

7643 Datasheet(PDF) 194 Page - Renesas Technology Corp

7643 Datasheet(HTML) 194 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL