7643 datasheet(198/424 Pages) RENESAS

198 / 424 page

Rev.2.00

Aug 28, 2006

page 77 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.5 DMAC

(2) DMAC channel x (x = 0, 1) mode register 1

•DMAC channel x source register increment/decrement selection bit (DxSRID)

•DMAC channel x source register increment/decrement enable bit (DxSRCE)

•DMAC channel x destination register increment/decrement selection bit (DxDRID)

•DMAC channel x destination register increment/decrement enable bit (DxDRCE)

These bits select that the DMAC channel X source registers and destination registers are either

decreased or increased by 1 after transfer completion.

•DMAC channel x data write control bit (DxDWC)

The DxDWC bit controls write operation to the following registers and their latches: Low and

High bytes of DMAC channel x source registers, destination registers and transfer count registers.

When the DxDWC bit is “0”, data is simultaneously written into each latch and register. When

this bit is “1”, data is written only into their latches.

•DMAC channel x disable after count register underflow enable bit (DxDAUE)

When the DxDAUE bit is “1”, after the DMAC channel x transfer count register Low underflows

the corresponding channel x is disabled. The DMAC channel x enable bit (DxCEN, bit 7 of

DMAxM2) goes to “0” at the same time.

•DMAC channel x register reload bit (DxRLD)

Writing “1” to the DxRLD bit can update the DMAC channel x source registers, destination

registers and transfer count registers with the values in their respective latches. It can be

performed at anytime. This bit is fixed to “0” at read.

•DMAC channel x transfer mode selection bit (DxTMS)

The DxTMS bit selects the transfer mode.

DMAC channel x mode register 1 (x = 0, 1)

b7 b6 b5 b4 b3 b2 b1 b0

DMAC channel x mode register 1

(DMAxM1 : address 4016) (Note 1)

Name

Functions

At reset R W

0 : Increment after transfer

1 : Decrement after transfer

0 : Disabled (No change after transfer)

1 : Enabled

DMAC channel x source

selection bit (DxSRID)

DMAC channel x source

enable bit (DxSRCE)

0 : Increment after transfer

1 : Decrement after transfer

0 : Disabled (No change after transfer)

1 : Enabled

DMAC channel x destination

selection bit (DxDRID)

DMAC channel x destination

enable bit (DxDRCE)

DMAC channel x data

write control bit (DxDWC)

0 : Writing data in reload latches and

registers

1 : Writing data in reload latches only

DMAC channel x disable after

count register underflow

enable bit (DxDAUE)

0 : Channel x enabled after count

1 : Channel x disabled after count

DMAC channel x register

reload bit (DxRLD)

0 : Not reloaded

1 : Source, destination, and transfer

count registers contents of channel x

to be reloaded

DMAC channel x transfer

mode selection bit (DxTMS)

0 : Cycle steal transfer mode

1 : Burst transfer mode

(Note 2)

Notes 1: Channels 1 and 2 share this register. The channel selection which can use this register

depends on channel index bit, bit 7 of DMAC index and status register.

2: These bits’ contents are “0” at read.

Fig. 2.5.3 Structure of DMAC channel x (x = 0, 1) mode register 1

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