7643 datasheet(228/424 Pages) RENESAS

228 / 424 page

Rev.2.00

Aug 28, 2006

page 107 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.6 USB

Fig. 2.6.10 Structure of USB interrupt status register 1

USB interrupt status register 1

b7 b6 b5 b4 b3 b2 b1 b0

USB interrupt status register 1

(USBIS1 : address 5216)

Name

Functions

At reset R W

USB endpoint 1 IN

interrupt status flag

(INTST2)

USB endpoint 1 OUT

interrupt status flag

(INTST3)

0 : Except the following conditions

1 : Set at any one of the following

conditions:

• A packet data of endpoint 0 is

successfully received

• A packet data of endpoint 0 is

successfully sent

• DATA_END bit of endpoint 0 is

cleared to “0”

• FORCE_STALL bit of endpoint 0 is

set to “1”

• SETUP_END bit of endpoint 0 is set

to “1”.

0 : Except the following conditions

1 : Set at which of the following

condition:

• A packet data of endpoint 1 is

successfully sent

USB endpoint 2 IN

interrupt status flag

(INTST4)

0 : Except the following conditions

1 : Set at which of the following

condition:

• A packet data of endpoint 2 is

successfully sent

USB endpoint 0 interrupt

status flag (INTST0)

Nothing arranged for this bit. Fix this bit to “0”.

Nothing arranged for these bits.

Fix these bits to “0”.

✽

0 : Except the following conditions

1 : Set at any one of the following

conditions:

• A packet data of endpoint 1 is

successfully received

• FORCE_STALL bit of endpoint 1 is set

to “1”.

USB endpoint 2 OUT

interrupt status flag

(INTST5)

✽

0 : Except the following conditions

1 : Set at any one of the following

conditions:

• A packet data of endpoint 2 is

successfully received

• FORCE_STALL bit of endpoint 2 is set

to “1”.

✽: “0” can be set by software, but “1” cannot be set.

To clear the bit set to “1”, write “1” to the bit.

(4)

USB interrupt status registers 1, 2

These registers are used to determine the state of a USB function interrupt source. When an

interrupt request occurs, the flag corresponding to the interrupt source is set to “1”.

After “1” is read from each flag in this register, they are cleared to “0” when the next “1” is written.

This flag is not cleared even if “0” is written. Make sure to write to/read from the USB interrupt

status register 1 first and then USB interrupt status register 2.

Figures 2.6.10 and 2.6.11 show the structures of USB interrupt status registers 1 and 2, respectively.

7643 Datasheet(PDF) 228 Page - Renesas Technology Corp

7643 Datasheet(HTML) 228 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL