7643 datasheet(232/424 Pages) RENESAS

232 / 424 page

Rev.2.00

Aug 28, 2006

page 111 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.6 USB

(7)

USB endpoint 0 IN control register

This register comprises the bits related to endpoint 0 control and status information.

q OUT_PKT_RDY flag

This flag is set to “1” when a valid SETUP/OUT token is received from the host CPU. After the

OUT FIFO is read, clear this flag to “0” by writing “1” to the SERVICED_OUT_PKT_RDY bit.

(However, do not clear this flag to “0” until the request from the host CPU has been completely

decoded.)

Nothing is changed even when writing “1” to this flag is executed.

q IN_PKT_RDY bit

Set this bit to “1” after writing one packet of data to the endpoint 0 IN FIFO. The USB FCU

clears this bit to “0” after an IN FIFO transmit or when the SETUP_END flag is set to “1”.

Nothing is changed even when writing “0” to this flag is executed.

q SEND_STALL bit

Set this bit to “1” when an invalid standard request is received from the host CPU. When the

OUT_PKT_RDY flag to receive the request is set to “0”, the USB FCU sends a STALL handshake

signal to the host CPU in response to all IN/OUT transactions.

Write “0” to this bit to clear it. If the OUT_PKT_RDY flag is “1” when the SEND_STALL bit is

set to “1”, the OUT_PKT_RDY flag can be cleared to “0” by setting the SERVICED_OUT_PKT_RDY

bit to “1”.

q DATA_END bit

When the last data is written to the FIFO (IN data phase) or the last data is read from the FIFO

(OUT data phase), set this bit to “1”. This informs the USB FCU that all data set in the setup

phase has been completely processed.

The USB FCU sets this bit to “0” automatically after the status phase process is completed.

When this bit is “1”, data receive and data transmit requests from the host are ignored. The USB

FCU sends a STALL handshake signal to the host CPU and completes the current control

operation.

q FORCE_STALL flag

This flag is set to “1” for an error report if any of the following conditions occur.

- An IN/OUT token is received which does not have a setup stage.

- An incorrect data toggle is received (DATA0) in the status stage.

- An incorrect data toggle is received (DATA1) in the setup stage.

- A request for more data than requested in the setup stage (an IN token is received after the

DATA_END bit is set).

- A data receive for more data than specified in the setup stage (an OUT token is received after

the DATA_END bit is set).

- More data is received than the number of bytes in the maximum packet size of the corresponding

endpoint.

Excluding the case in which an incorrect data toggle occurs in the setup stage, when one of the

above conditions occurs, a STALL is sent in response to the problematic IN/OUT token. When

there is an incorrect data toggle in the setup stage, an ACK is returned in response to the setup

stage, and a STALL is returned in response to the next IN/OUT token. The generated STALL

handshake is transmitted in response to only one transaction, and the control transfer in process

is completed. The next packet received after the STALL handshake is recognized as the beginning

of a new control transfer.

Write “0” to this flag to clear it.

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