7643 datasheet(234/424 Pages) RENESAS

234 / 424 page

Rev.2.00

Aug 28, 2006

page 113 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.6 USB

(8) USB endpoint 1, 2 IN control register

These registers comprise bits related to endpoints 1 and 2 control and status information.

q IN_PKT_RDY bit

Single-buffer mode:

Set this bit to “1” after writing one packet of data to the IN FIFO (this bit is automatically set

to “1” when AUTO_SET bit is “1”).

The USB FCU clears this bit to “0” when the IN FIFO transmit is completed (after the ACK is

received from the host).

Double-buffer mode:

Set this bit to “1” every writing one packet of data to the IN FIFO. After writing one packet of

data, if there is one packet in the FIFO, the IN_PKT_RDY bit is not set to “1”; only the TX_NOT_EPT

flag is set to “1”. If the FIFO has two packets (FIFO full state) after the write, both the IN_PKT_RDY

bit and TX_NOT_EPT flag are set to “1” (refer to Table 2.6.2).

The USB FCU clears this bit to “0” when the IN FIFO transmit is completed (after the ACK is

received from the host).

Nothing is changed even when writing “0” to this flag is executed. When you need to access this

bit in a case such as setting other bits in the endpoint x IN control register is performed, clear

this bit to “0” by program.

q SEND_STALL bit

Set this bit to “1” in the STALL state. When this bit is “1”, the USB FCU sends a STALL

handshake signal to the host CPU.

q TOGGLE_INIT bit

This bit initializes the toggle sequence bit.

Setting the TOGGLE_INIT bit to “1” assigns the PID of the next packet of data to be transmitted

to the host as DATA0. To initialize the data toggle sequence bit for an endpoint (reset the next

data packet as DATA0), set this bit to “1” and then clear it to “0”.

q INTPT bit

Set this bit to “1” in order to use an IN endpoint for rate feedback interrupt transfer, as described

in detail below.

1. Set the USB endpoint x IN maximum packet size register to a value larger than 1/2 the USB

endpoint x FIFO size.

2. Set the INTPT bit to “1”.

3. Flush out the old data in the FIFO.

4. Store the transmit data in the IN FIFO and set IN_PKT_RDY bit to “1”.

5. Repeat steps 3 and 4.

When using the endpoint for rate feedback interrupt transfer in an actual application, the function-

side always must have transmit data to send to the host. Therefore, in a rate feedback interrupt

transfer, the device never returns a NAK in response to the IN token from the host. The device

transmits the data in the FIFO in response to an IN token regardless of the IN_PKT_RDY status.

However, this function in the 7643 Group assumes that there is an ACK response from the host

after data is transmitted in response to an IN token.

q TX_NOT_EPT flag

This flag is set to “1” when there is data in the IN FIFO.

q FLUSH bit

Set this bit to “1” in order to erase the data in the FIFO. If there are two or more packets in the

IN FIFO, the old data will be erased. Setting this bit to “1” during a USB transfer may cause the

transmit data to be erased.

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