7643 datasheet(236/424 Pages) RENESAS

236 / 424 page

Rev.2.00

Aug 28, 2006

page 115 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.6 USB

Fig. 2.6.14 Structure of USB endpoint x IN control register

AUTO_SET bit (INXCSR7) 0 : AUTO_SET disabled

1 : AUTO_SET enabled ✽3

SERVICED_SETUP_END

bit (IN0CSR7)

0 : Except the following condition

1 : Writing “1” to this bit clears SETUP_

END flag to “0”.

USB endpoint 0 IN control register

b7 b6 b5 b4 b3 b2 b1 b0

USB endpoint 0 IN control register

(IN_CSR : address 5916)

Name

Functions

At reset R W

IN_PKT_RDY bit

(IN0CSR1)

DATA_END bit (IN0CSR3)

FORCE_STALL flag

(IN0CSR4)

SEND_STALL bit

(IN0CSR2)

0 : Except the following condition

(Cleared to “0” by writing “1” into

SERVICED_OUT_PKT_RDY bit)

1 : End of a data packet reception

0 : End of a data packet transmission

1 : Write “1” at completion of writing a

data packet into IN FIFO.

0 : Except the following condition

1 : Transmitting STALL handshake signal

0 : Except the following condition

(Cleared to “0” after completion of

status phase)

1 : Write “1” at completion of writing or

reading the last data packet to/from

FIFO.

0 : Except the following condition

1 : Protocol error detected

SETUP_END flag

(IN0CSR5)

0 : Except the following condition

(Cleared to “0” by writing “1” into

SERVICED_SETUP_END bit)

1 : Control transfer ends before the

specific length of data is transferred

during the data phase.

SERVICED_OUT_PKT_R

DY bit (IN0CSR6)

0 : Except the following condition

1 : Writing “1” to this bit clears OUT_

PKT_RDY flag to “0”.

OUT_PKT_RDY flag

(IN0CSR0)

USB endpoint 1, 2 IN control register

b7 b6 b5 b4 b3 b2 b1 b0

USB endpoint 1, 2 IN control register

(IN_CSR : address 5916)

Name

Functions

At reset R W

SEND_STALL bit

(INXCSR2)

TOGGLE_INIT bit

(INXCSR3)

0 : End of a data packet transmission

1 : Write “1” at completion of writing a

data packet into IN FIFO. (Note 2)

0 : Except the following condition

1 : Transmitting STALL handshake signal

0 : Except the following condition

1 : Initializing the data toggle sequence

bit

INTPT bit (INXCSR4)

0 : Except the following condition

1 : Initializing to endpoint used for

interrupt transfer, rate feedback

TX_NOT_EPT flag

(INXCSR5)

0 : Empty in IN FIFO

1 : Full in IN FIFO

FLUSH bit (INXCSR6)

0 : Except the following condition

1 : Flush FIFO

INT_PKT_RDY bit

(INXCSR0) ✽1

✽ 1: “1” can be set by software, but “0” cannot be set.

✽ 2: When INXCSR7=“1”, this bit is automatically set to “1”.

When INXCSR7=“0”, writing data to FIFO, and then write “1” to this bit.

✽ 3: To use the AUTO_SET function for an IN transfer when the AUTO_SET bit is set to “1”,

set the FIFO to single buffer mode.

Nothing is arranged for this bit.

Fix this bit to “0”.

✽2

✽1

✽2

✽1

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