7643 datasheet(240/424 Pages) RENESAS

240 / 424 page

Rev.2.00

Aug 28, 2006

page 119 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.6 USB

Fig. 2.6.17 Structure of USB endpoint x (x=0 to 2) OUT max. packet size register

USB endpoint x OUT max. packet size register

b7 b6 b5 b4 b3 b2 b1 b0

USB endpoint x OUT max. packet size register

(OUT_MAXP: address 5C16)

(Note)

Functions

At reset R W

(Note)

The maximum packet size (MAXP) of endpoint x OUT is contained.

qMAXP = n for endpoints 0, 2

qMAXP = n ✕ 8 for endpoint 1

“n” is a written value into this register.

Note: The value is “0816” in the endpoint 0 or 2 used.

The value is “0116” in the endpoint 1 used.

(11) USB endpoint x (x = 0 to 2) OUT max. packet size register

This register specifies the maximum packet size (MAXP) of an endpoint x (x = 0 to 2) OUT

packets. Modify the contents of this register when the SET_DESCRIPTOR command is received

from the host CPU. The OUT maximum packet sizes (MAXP) are as follows:

- When using endpoint 2: MAXP = n

- When using endpoint 1: MAXP = n*8 (n: the value set in this register)

When not using this register, clear “0” to this register.

When using the endpoint 0, both USB endpoint x IN max. packet size register (IN _MAXP) and

USB endpoint x OUT max. packet size register (OUT_MAXP) are set to the same value. Changing

one register’s value effectively changes the value of the other register as well.

If the maximum packet size is larger than 1/2 the FIFO size, one packet of data can be stored in

the FIFO (single-buffer). If the maximum packet size is less than 1/2 the FIFO size, two packets

can be stored (double-buffer).

Figure 2.6.17 shows the structure of the USB Endpoinx (x = 0 to 2) OUT max. packet size register.

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