7643 datasheet(244/424 Pages) RENESAS

244 / 424 page

Rev.2.00

Aug 28, 2006

page 123 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.6 USB

Fig. 2.6.22 Structure of frequency synthesizer control register

Frequency synthesizer control register

b7 b6 b5 b4 b3 b2 b1 b0

Frequency synthesizer control register

(FSC : address 6C16)

Name

Functions

At reset R W

Frequency synthesizer

input bit (FIN)

LPF current control bit

(CHG1, CHG0) (Note)

0 : Disabled

1 : Enabled

0 : f(XIN)

1 : f(XCIN)

Frequency synthesizer

lock status bit

0 : Unlocked

1 : Locked

Frequency synthesizer

enable bit (FSE)

Nothing is arranged for this bit.

Fix this bit to “0”.

Nothing is arranged for these bits.

Fix these bits to “0”.

b1b0

0 0 : Not available

0 1 : Low current

1 0 : Intermediate current (recommended)

1 1 : High current

Note: Bits 6 and 5 are set to (bit 6, bit 5) = (1, 1) at reset.

When using the frequency synthesizer, we recommend to set to (bit 6, bit 5) = (1, 0) after

locking the frequency synthesizer.

(16) Frequency synthesizer control register

This register performs all controls related to the frequency synthesizer, which generates fUSB and

fSYN from f(XIN).

q Frequency synthesizer enable bit

Set this bit to “1” to use the frequency synthesizer.

q Frequency synthesizer input bit

When this bit is “0”, f(XIN) is used as the frequency synthesizer input.

When “1”, f(XCIN) is used.

q LPF current control bit

Bits 6 and 5 = “11” when reset is released.

To use the frequency synthesizer, make sure to specify bits 6 and 5 to “10” after the frequency

synthesizer is locked.

q Frequency synthesizer lock status bit

When this bit is set to “1”, it indicates that both fSYN and fVCO have stabilized.

Figure 2.6.22 shows the structure of the frequency synthesizer control register.

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