7643 datasheet(242/424 Pages) RENESAS

242 / 424 page

Rev.2.00

Aug 28, 2006

page 121 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.6 USB

Fig. 2.6.19 Structure of USB endpoint x (x=0 to 2) FIFO register

Fig. 2.6.20 Structure of USB endpoint FIFO mode register

USB endpoint x FIFO register

b7 b6 b5 b4 b3 b2 b1 b0

USB endpoint x (x=0 to 2) FIFO register

(USBFIFOx: addresses 6016, 6116, 6216)

Undefined

Functions

At reset R W

Undefined

qThis is Endpoint x IN/OUT FIFO.

qWrite a data to be transmitted into this IN FIFO.

qRead a received data from this OUT FIFO.

USB endpoint FIFO mode register

b7 b6 b5 b4 b3 b2 b1 b0

USB endpoint FIFO mode register

(USBFIFOMR : address 5F16)

Name

Functions

At reset R W

For endpoint 1

b3b2b1b0

✕ 0 0 0 : IN 128-byte, OUT 128-byte

For endpoint 2

b3b2b1b0

0 ✕ ✕ ✕ : IN 32-byte, OUT 32-byte

1 ✕ ✕ ✕ : IN 128-byte, OUT 128-byte

FIFO size selection bit

(Note)

Note: The value set into “x” is invalid.

Nothing is arranged for these bits. When these bits are read out, the

contents are undefined. These bits are “0” at write.

(13) USB endpoint x (x = 0 to 2) FIFO register

These registers are the USB IN (transmit) and OUT (receive). Write data to the corresponding

to or less than 1/2 the FIFO size, these registers function in double buffer mode and can hold two

packets of data.

Figure 2.6.19 shows the structure of the USB endpoint x (x = 0 to 2) FIFO register.

(14) USB endpoint FIFO mode register

This register determines the IN/OUT FIFO size mode for endpoint 1 or endpoint 2.

Figure 2.6.20 shows the structure of the USB endpoint x FIFO mode register.

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