7643 datasheet(243/424 Pages) RENESAS

243 / 424 page

Rev.2.00

Aug 28, 2006

page 122 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.6 USB

Fig. 2.6.21 Structure of clock control register

Clock control register

b7 b6 b5 b4 b3 b2 b1 b0

Clock control register

(CCR : address 1F16)

Name

Functions

At reset R W

0 : XCOUT oscillation drive is enabled.

(When XCIN oscillation is enabled.)

1 : XCOUT oscillation drive is disabled.

XCOUT oscillation drive

disable bit (CCR5)

0 : XOUT oscillation drive is enabled.

(When XIN oscillation is enabled.)

1 : XOUT oscillation drive is disabled.

XOUT oscillation drive

disable bit (CCR6)

XIN divider select bit

(CCR7) (Note)

Note: This bit is valid when (b7, b6 of CPMA) = “00”.

0 : f(XIN)/2 is used for the system clock.

1 : f(XIN) is used for the system clock.

Nothing is arranged for these bits.

Fix these bits to “0”.

(15) Clock control register

This register controls all oscillators.

The XIN divider select bit is valid when CPMA6 and CPMA7 = “00”

When “0”: f(XIN)/4 is the internal

φ clock.

When “1”: f(XIN)/2 is the internal

φ clock.

Note that this bit is cleared to “0” by execution of the STP instruction.

Figure 2.6.21 shows the structure of the clock control register.

7643 Datasheet(PDF) 243 Page - Renesas Technology Corp