7643 datasheet(245/424 Pages) RENESAS

245 / 424 page

Rev.2.00

Aug 28, 2006

page 124 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.6 USB

2.6.4 USB transmit

Endpoint 0 to endpoint 2 have IN (transmit) FIFOs individually.

Each endpoint’s FIFO is configured in following way:

Endpoint 0: 16-byte

Endpoint 1: 128-byte

Endpoint 2: Mode 0: 32-byte

Mode 1: 128-byte

When endpoint 2 is used, the IN FIFO size differs according to the mode.

To select the mode, use the USB endpoint FIFO mode register (address 005F16).

USB transmit data is written to the USB endpoint x (x = 0 to 2) FIFO (addresses 006016 to 006216). When

data is written to this register, the internal Write pointer is automatically incremented by 1. The contents

of the internal Write pointer cannot be read out, and the contents of the FIFO are undefined at reset.

q When using endpoint 0

Set the IN_PKT_RDY bit to “1” after writing transmit data to the IN FIFO. The IN_PKT_RDY bit

is set to “0” automatically after one packet of data is transmitted or when the SETUP_END flag

is set to “1”.

When using endpoint 0, set the DATA_END bit to “1” when the last data packet has been written

to the IN FIFO. When the DATA_END bit is set to “1”, the USB FCU will go on to the next phase

process and clear the bit to “0”.

q When using endpoints 1, 2

When max. packet size is greater than 1/2 (single buffer)

- When AUTO_SET bit = “1”

The IN_PKT_RDY bit (and TX_NOT_EPT flag) is automatically set to “1” when the number of

bytes of data written to the IN FIFO equals the value set in the endpoint x IN max. packet size

- When AUTO_SET bit = “0” or when a short packet (smaller than max. packet size) is transferred

Set the IN_PKT_RDY bit to “1” by software.

When max. packet size is less than or equal to 1/2 (double buffer)

Set the IN_PKT_RDY bit to “1” by software after one packet has been written to the IN FIFO.

When one packet data is set in the IN FIFO and there is only one packet stored in the IN FIFO,

the IN_PKT_RDY bit is set to “1”. However, it is cleared after 83ns (when f(XIN) = 24MHz, Vcc

= 5 V), and the TX_NOT_EPT flag then is set to “1”. If there are already two packets in the IN

FIFO (IN FIFO full), both the IN_PKT_RDY bit and the TX_NOT_EPT flag are set to “1”.

In the single-buffer mode, the IN_PKT_RDY bit and the TX_NOT_EPT flag will be automatically cleared

to “0” after completion of the transmission.

In the double-buffer mode, if there is no data in the IN FIFO, the IN_PKT_RDY bit and the TX_NOT_EPT

flag will be automatically cleared to “0” after completion of the transmission. If there is one packet data

already in the IN FIFO, the IN_PKT_RDY bit will be set to “0” after completion of the transmission, but

the TX_NOT_EPT flag will remain at “1”.

The USB transmit default mode is the bulk transfer.

To use any other transfer mode, the user needs to initialize the corresponding endpoints.

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