7643 datasheet(247/424 Pages) RENESAS

247 / 424 page

Rev.2.00

Aug 28, 2006

page 126 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.6 USB

2.6.5 USB receive

Endpoint 0 to endpoint 2 have OUT (transmit) FIFOs individually.

Each endpoint’s FIFO is configured in following way:

Endpoint 0: 16-byte

Endpoint 1: 128-byte

Endpoint 2: Mode 0: 32-byte

Mode 1: 128-byte

When endpoint 2 is used, the OUT FIFO size differs according to the mode.

To select the mode, use the USB endpoint FIFO mode register (address 005F16).

USB receive data is read from the USB endpoint x (x = 0 to 2) OUT FIFO.

When data is read from this register, the internal Write pointer is automatically decremented by 1.

The contents of the internal Write pointer cannot be read out, and the contents of the FIFO are undefined at reset.

When using endpoint 0

When a receive is completed, the OUT_PKT_RDY flag is set to “1” and the number of receive data

is set in the USB endpoint x (x = 0 to 2) OUT write count register (address 005D16). After data is

read from the OUT FIFO, clear the OUT_PKT_RDY flag to “ 0 ” by writing “ 1 ” to the

SERVICED_OUT_PKT_RDY bit. When using endpoint 0, set the DATA_END bit to “1” after the last

data packet is read from the OUT FIFO. When the DATA_END bit is set to “1”, the USB FCU will

go on to the next phase process and clear the bit to “0”.

When using endpoints 1, 2

When a receive is completed, the OUT_PKT_RDY flag is set to “1” and the number of bytes of

receive data is set in the USB endpoint x (x = 0 to 2) OUT write count register (address 005D16).

When max. packet size is greater than 1/2 (single-buffer)

- When AUTO_CLR bit = “1”

When data (the size equals received OUT packet) is read from the OUT FIFO, the OUT_PKT_RDY

flag is automatically cleared to “0”.

- When AUTO_CLR bit = “0”

The user needs to clear the OUT_PKT_RDY flag through software.

When max. packet size is less than or equal to 1/2 (double-buffer)

- When AUTO_CLR bit = “1”

When data (the size equals received OUT packet) is read from the OUT FIFO but there is no data

in the OUT FIFO, the OUT_PKT_RDY flag automatically is set to “0”. If there is one packet of

data in the OUT FIFO, OUT_PKT_RDY flag will be cleared to “0” but then set to “1” after 83ns

(when f(XIN) = 24MHz, Vcc = 5 V).

- When AUTO_CLR bit = “0”

Clear the OUT_PKT_RDY flag to “0” after reading data from the OUT FIFO (it will not be cleared

automatically). When there is no data in the OUT FIFO, the OUT_PKT_RDY flag will be set to

“0”. If there is one packet of data in the OUT FIFO, OUT_PKT_RDY flag is cleared to “0” once,

then set to “1” after 83ns (when f(XIN) = 24MHz, Vcc = 5 V).

(1) Usage notes concerning data receive

q OUT_PKT_RDY flag

Read one packet data from the OUT FIFO before clearing the OUT_PKT_RDY flag. If the

OUT_PKT_RDY flag is cleared while one packet data is being read, the internal Read pointer

cannot operate normally.

q OUT FIFO

For endpoints 1 or 2, when there are two packets of data in the OUT FIFO, after reading out the

max OUT packet size of data, one packet of data will remain in the OUT FIFO. In this case, even

if the OUT_PKT_RDY flag is set to “0”, it will return to “1” after 83ns (Vcc = 5V, f(XIN) = 24MHz).

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