7643 datasheet(237/424 Pages) RENESAS

237 / 424 page

Rev.2.00

Aug 28, 2006

page 116 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.6 USB

(9)

USB endpoint x (x = 1, 2) OUT control registers

When using endpoint 0, these registers are the reserved registers and cannot be assigned to any

function.

q OUT_PKT_RDY flag

This flag is set to “1” when a data receive from the host CPU is completed. Clear the flag to

“0” after the data is read from the OUT FIFO. This flag is automatically cleared to “0” when the

AUTO_CLR bit is “1”. To avoid internal Read pointer malfunction, do not clear the flag to “0” until

reading out one packet of data from the host is completed. The value of the USB endpoint x

OUT write count register is updated when this flag is cleared.

When two or more data packets are written to the OUT FIFO in the double-buffer mode, the flag

is set to “0” if “0” is written to it after one packet of data is read, but returns to “1” after 83ns

(Vcc = 5V, f(XIN) = 24MHz).

USB operations are not affected by writing “1” to this flag. Write “1” to the OUT_PKT_RDY flag

to access it.

q SEND_STALL bit

Set this bit to “1” in the STALL state. When this bit is “1”, the USB FCU sends a STALL

handshake signal to the host CPU.

q TOGGLE_INIT bit

This bit initializes the toggle sequence bit.

Setting the TOGGLE_INIT bit to “1” assigns the PID of the next packet received from the host

as DATA0. To initialize the data toggle sequence bit of an endpoint (reset the next data packet

as DATA0), set this bit to “1” and then clear it to “0”.

q FORCE_STALL flag

This flag is set to “1” when data received from the host CPU is larger than the max. OUT packet

size. The USB FCU then sends a STALL handshake signal to the host CPU. Write “0” to this

flag to clear it.

q FLUSH bit

Set this bit to “1” to erase the data in the OUT FIFO. When there are two or more packets of

data in the OUT FIFO, the old data will be erased. Setting this bit to “1” during a transfer may

cause the receive data to be erased. When setting the OUT_PKT_RDY flag to “1”, also set this

bit to “1”.

q AUTO_CLR bit

When this bit is “1” and the size of the data read from the OUT FIFO matches that of the

received OUT packet, the OUT_PKT_RDY flag is automatically cleared to “0”.

Figure 2.6.15 shows the structure of the USB endpoint x (x = 1, 2) OUT control register.

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