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7643 Datasheet(PDF) 230 Page - Renesas Technology Corp |
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7643 Datasheet(HTML) 230 Page - Renesas Technology Corp |
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230 / 424 page ![]() Rev.2.00 Aug 28, 2006 page 109 of 202 7643 Group REJ09B0133-0200 APPLICATION 2.6 USB Fig. 2.6.12 Structure of USB interrupt enable register 1, USB interrupt enable register 2 1 USB interrupt enable register 1 b7 b6 b5 b4 b3 b2 b1 b0 USB interrupt enable register 1 (USBIE1 : address 5416) b 0 0 2 4 Name 1 Functions At reset R W 1 1 1 1 USB endpoint 1 IN interrupt enable bit (INTEN2) USB endpoint 1 OUT inter- rupt enable bit (INTEN3) 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled USB endpoint 2 OUT inter- rupt enable bit (INTEN5) 5 ✕ 6 7 ✕ USB endpoint 0 interrupt enable bit (INTEN0) 3 USB endpoint 2 IN interrupt enable bit (INTEN4) 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled Nothing is arranged for these bits. When these bits are read out, the contents are undefined. These bits are “0” at write. Nothing arranged for this bit. Fix this bit to “0”. 1 0 Nothing is arranged for these bits. Fix these bits to “0”. USB interrupt enable register 2 b7 b6 b5 b4 b3 b2 b1 b0 USB interrupt enable register 2 (USBIE2 : address 5516) b 0 0 0 1 0 1 2 4 Name ✕ Functions At reset R W ✕ 0 ✕ 7 0 3 1 Nothing is arranged for this bit. Fix this bit to “1”. Nothing is arranged for this bit. Fix this bit to “0”. 5 0 6 USB suspend/resume interrupt enable bit (INTEN15) 0 : Disabled 1 : Enabled Nothing is arranged for this bit. When this bit is read out, the contents are undefined. This bit is “0” at write. Nothing is arranged for this bit. When this bit is read out, the contents are undefined. This bit is “0” at write. (5) USB interrupt enable registers 1, 2 The USB interrupt enable registers are used to enable the USB function interrupt. Upon reset, all USB interrupts except the USB suspend and USB resume interrupts are enabled. The USB reset interrupt does not have an enable bit and is always in the enabled state. Figures 2.6.12 shows the structures of USB interrupt enable registers 1 and 2. |
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