7643 datasheet(269/424 Pages) RENESAS

269 / 424 page

Rev.2.00

Aug 28, 2006

page 148 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.6 USB

Fig. 2.6.43 Connection diagram

URXD

RTS

General purpose

port 1

General purpose

port 2

P84/UTXD

P86/CTS

P41/INT0

P40

USB

USB OUT

7643 Group

Host CPU

Receiving side

Transmitting side

Transfer

Host PC

2.6.8 Connection with other functions

The 7643 Group also has DMAC and UART connections for USB transfers, enabling high-volume data

transfers.

(1)

Application example 1: Data packet transfer from USB FIFO to UART (without DMA)

Outline: Data is transmitted from USB FIFO to host CPU using UART.

Specification: - USB endpoint 1 OUT bulk transfer is used.

- USB endpoint 1 OUT interrupt is used.

- USB endpoint 1 OUT packet size: 64 bytes

- UART transmit is used.

- UART transmit interrupt (when transmit shift operation is completed) is used.

- Transfer bit rate: 9600bps (

φ = 12MHz divided by 1248)

- Data format: 1ST-8DATA-1SP

- Parity bit is disabled

- Re-transmit is executed if transfer error occurs (re-transmit in byte unit)

-P41/INT0 pin is used to detect the re-transmit request (host CPU sets P41/INT0

pin to “L” when UART receive error occurs)

- INT0 interrupt request flag (falling edge) to detect the re-transmit request is used.

-P40 to inform host CPU of USB packet transmit is used.

- CTS function is used.

After USB data is received from the host PC, the 7643 MCU stores the value of the USB endpoint

1 OUT write count register (number of received bytes) in Storage RAM 1 by the USB endpoint 1

OUT interrupt. Then, sets P40 to “L”, the UART transmit interrupt to be enabled, and starts the

UART transmit.

As soon as the UART transmit is enabled, the first UART transmit interrupt occurs. Therefore, the

7643 MCU writes one byte of the received USB FIFO data to both Storage RAM2 and UART

transfer buffer register 1, and returns from the interrupt. Next, the host CPU sets the CTS pin to

“L” and reads the data in the UART transmit/receive shift register. At this time, since another UART

transfer interrupt occurs, the same process is repeated until the USB FIFO is empty.

On the other hand, when the host CPU requests a re-transmit by a UART receive error etc., it is

programmed to set the P41/INT0 pin to “L”. In the 7643 Group, the data in Re-transmit RAM 2 is

written to the UART transmit/receive buffer register if the INT0 interrupt request flag is “1” in the

UART transmit interrupt routine. By this action, the previous data is resent to the host CPU.

As described above, when all data in the USB FIFO are transmitted to the host CPU, P40 is set

to “H”, the UART transmit interrupt is disabled, and the OUT_PKT_RDY flag of USB endpoint 1

OUT is cleared. This makes USB endpoint 1 ready to receive the next USB data packet.

Figure 2.6.43 shows the connection diagram, Figures 2.6.44 to 2.6.46 show related register settings,

and Figures 2.6.47 and 2.6.48 show control procedure examples.

7643 Datasheet(PDF) 269 Page - Renesas Technology Corp

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