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7643 Datasheet(PDF) 271 Page - Renesas Technology Corp |
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7643 Datasheet(HTML) 271 Page - Renesas Technology Corp |
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271 / 424 page  Rev.2.00 Aug 28, 2006 page 150 of 202 7643 Group REJ09B0133-0200 APPLICATION 2.6 USB Fig. 2.6.45 Register setting (2) φ = system clock/2, system clock = f(XIN) Clock control register (Address : 1F16) CCR 0 0 0 0 0 1 Frequency synthesizer multiply register 1 (Address : 6D16) 0016 FSM1 b0 b7 b0 b7 Frequency synthesizer control register (Address : 6C16) FSC Frequency synthesizer : enabled Frequency synthesizer input : f(XIN) 0 b0 b7 01 Frequency synthesizer multiply register 2 (Address : 6E16) FF16 FSM2 b0 b7 0016 FSD 1 000 0 Frequency synthesizer divide register (Address : 6F16) Port P4 direction register (Address : 1916) P4D P40: output b0 b7 P41: input 1 0 Interrupt polarity select register (Address : 1116) IPOL INT0 interrupt edge : Falling edge b0 b7 0 b0 b7 |
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