7643 datasheet(274/424 Pages) RENESAS

274 / 424 page

Rev.2.00

Aug 28, 2006

page 153 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.6 USB

Wait the processing of Host CPU error

detection is completed.

UART transmit interrupt

• Re-transmit

When re-transmit request occurs,

the previous value is re-transmitted.

RAM2

UTRB1

RAM1

XXXXXXX02

(Address : 6116)

RAM2

(Address : 1816)

USBFIFO1

(Address : 3416)

RAM1 – 1

Re-transmit request cleared

RTI

Pop registers

• End processing

UART transmit interrupt disabled

USB receive (OUT) enabled

Push registers to stack

Host CPU detects error and waits until host CPU operates INT0.

* Wait time here depends on processing by Host CPU.

Check of INT0 interrupt request flag.

Re-transmit requested ?

XXXXXXX12

(Address : 1816)

RAM1 > 0?

RAM1=“0”?

ICONA

USBINDEX

OUT_CSR

X00000012

0XXXXXX12

(Address : 0516), bit7

(Address : 5816)

(Address : 5A16)

UTRB1 (Address 3416)

Interrupt occurs

• INT0 interrupt request flag is cleared.

P40 is “H”

• Writing data

P40 is “L”

Writing to UART

RAM2

Fig. 2.6.48 Control procedure (2)

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