7643 datasheet(273/424 Pages) RENESAS

273 / 424 page

Rev.2.00

Aug 28, 2006

page 152 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.6 USB

CCR (Address : 1F16)

FSM1 (Address : 6D16)

FSM2 (Address : 6E16)

FSD (Address : 6F16)

FSC (Address : 6C16)

USBC (Address : 1316)

USBFIFOMR (Address : 5F16)

USBIE1 (Address : 5416)

USBINDEX (Address : 5816)

OUT_MAXP (Address : 5C16)

OUT_CSR (Address : 5A16)

UBRG (Address : 3116)

UMOD (Address : 3016)

UCON (Address : 3316)

P4 (Address : 1816)

P4D (Address : 1916)

IPOL (Address : 1116)

ICONA (Address : 0516)

IREQA (Address : 0216)

.....

8016

0016

FF16

0016

4116

1X1100X02

XXXXXX002

000010012

X00000012

0816

0XXXXXX12

4D16

010X00002

0011X0002

XXXXXXX12

XXXXXX012

XXXXXXX02

0XXXXXX12

0016

RESET

Endpoint 1 FIFO : OUT128 bytes

Endpoint 0, Endpoint 1OUT interrupt enabled

Max. packet size : 64 bytes

...

• UART initializing

φ as UART clock, 1 stop bit,

Parity checking disabled, 8-bit character length

CTS function enabled, RTS function disabled

Tramsmit interrupt source : Transmit shift completed

• Others

P40 : output, P41 : input

USB function interrupt : enabled

UART transmit interrupt : disabled

.....

USBIS1 (Address : 5216),bit3

USBINDEX (Address : 5816)

RAM1

WRT_CNT (Address : 5D16)

UCON (Address : 3316),bit2

UCON (Address : 3316),bit0

ICONA (Address : 0516),bit7

IREQA (Address : 0216),bit2

X00000012

Push registers to stack

* When USBINDEX is set, push its data to temporary buffer, and

return the data to USBINDEX after interrupt is completed.

USB endpoint 1 OUT interrupt

Pop registers

RTI

Interrupt occurs

Refer to the USB initiral setting.

• USB initializing

(Interrupt disabled)

Initialization

q x: This bit is not used here. Set it to “0” or “1” arbitrarily.

(interrupt enabled)

• Start processing

Number of USB receive bytes

UART transmit initializing

UART transmit enabled

UART transmit interrupt enabled

* Interrupt request flag is set as soon as

UART transmit interrupt is enabled.

•INT0 interrupt request bit set to “0”

Fig. 2.6.47 Control procedure (1)

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