7643 datasheet(289/424 Pages) RENESAS

289 / 424 page

Rev.2.00

Aug 28, 2006

page 168 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.7 PLL

2.7.2 Related registers

Fig. 2.7.2 Structure of CPU mode register A

CPU mode register A

b7 b6 b5 b4 b3 b2 b1 b0

CPU mode register A

(CPMA : address 0016)

Name

Functions

At reset R W

Stack page select bit

Sub-clock (XCIN-XCOUT)

stop bit

Main clock (XIN-XOUT) stop

bit

b1b0

0 0 : Single-chip mode

0 1 : Memory expansion mode

1 0 : Microprocessor mode (Note 1)

1 1 : Not available

0 : Page 0

1 : Page 1

0 : Stopped

1 : Oscillating

Internal system clock

select bit (Note 2)

0 : External clock (XIN-XOUT or XCIN-XCOUT)

1 : fsyn

External clock select bit

0 : XIN-XOUT

1 : XCIN-XCOUT

Processor mode bits

Nothing is arranged for this bit.

Fix this bit to “1”.

0 : Oscillating

1 : Stopped

Notes 1: This is not available in the flash memory version.

2: When (CPMA 7, 6) = (0, 0), the internal system clock can be selected between

f(XIN) and f(XIN)/2 by CCR7.

The internal clock

φ is the internal system clock divided by 2.

Frequency synthesizer control register

b7 b6 b5 b4 b3 b2 b1 b0

Frequency synthesizer control register

(FSC : address 6C16)

Name

Functions

At reset R W

Frequency synthesizer

input bit (FIN)

LPF current control bit

(CHG1, CHG0) (Note)

0 : Disabled

1 : Enabled

0 : f(XIN)

1 : f(XCIN)

Frequency synthesizer

lock status bit

0 : Unlocked

1 : Locked

Frequency synthesizer

enable bit (FSE)

Nothing is arranged for this bit.

Fix this bit to “0”.

Nothing is arranged for these bits.

Fix these bits to “0”.

b1b0

0 0 : Not available

0 1 : Low current

1 0 : Intermediate current (recommended)

1 1 : High current

Note: Bits 6 and 5 are set to (bit 6, bit 5) = (1, 1) at reset.

When using the frequency synthesizer, we recommend to set to (bit 6, bit 5) = (1, 0) after

locking the frequency synthesizer.

Fig. 2.7.3 Structure of Frequency synthesizer control register

7643 Datasheet(PDF) 289 Page - Renesas Technology Corp

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