7643 datasheet(293/424 Pages) RENESAS

293 / 424 page

Rev.2.00

Aug 28, 2006

page 172 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.7 PLL

(2) fVCO

fVCO is generated by multiplying fPIN by the contents of frequency synthesizer multiply register 1

(FSM1: address 6D16), where

fVCO = fPIN ✕ {2(n + 1)}, n: value set to FSM1.

Set the value of FSM1 so that fVCO will be 48 MHz.

fVCO is optimized in the frequency synthesizer to be used as fUSB and it will be sent into the USB

function control unit.

While the frequency synthesizer enable bit is “0” (disabled), fVCO retains “H” or “L” level.

Figure 2.7.9 shows the frequency synthesizer multiply register 1 setting example.

Fig. 2.7.9 Frequency synthesizer multiply register 1 setting example

2 MHz

4 MHz

6 MHz

12 MHz

24 MHz

Decimal

Hexadecimal

fVCO

48.00 MHz

0B16

0516

0316

0116

0016

fPIN

FSM1 register set value

(3) fSYN

fVCO is divided by the contents of frequency synthesizer divide register (FSD: address 6F16) to

generate fSYN, where

fSYN = fVCO / 2(m + 1), m: value set to FSD.

When the value of FSD is set to 255, the division is not performed and fSYN becomes invalid.

fSYN can be used as the internal system clock by setting the internal system clock select bit of CPU

mode register A.

Figure 2.7.10 shows the frequency synthesizer divide register setting example.

When the frequency synthesizer lock status bit is “1” in the frequency synthesizer enabled, this

indicates that fSYN and fVCO have correct frequencies.

48.00 MHz

Decimal

127

Hexadecimal

0016

24.00 MHz

fSYN

187.5 kHz

7F16

fVCO

FSD register set value

Fig. 2.7.10 Frequency synthesizer divide register setting example

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