7643 datasheet(296/424 Pages) RENESAS

296 / 424 page

Rev.2.00

Aug 28, 2006

page 175 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.8 External device connection

2.8.2 Related registers

Fig. 2.8.2 Structure of CPU mode register A

CPU mode register A

b7 b6 b5 b4 b3 b2 b1 b0

CPU mode register A

(CPMA : address 0016)

Name

Functions

At reset R W

Stack page select bit

Sub-clock (XCIN-XCOUT)

stop bit

Main clock (XIN-XOUT) stop

bit

b1b0

0 0 : Single-chip mode

0 1 : Memory expansion mode

1 0 : Microprocessor mode (Note 1)

1 1 : Not available

0 : Page 0

1 : Page 1

0 : Stopped

1 : Oscillating

Internal system clock

select bit (Note 2)

0 : External clock (XIN-XOUT or XCIN-XCOUT)

1 : fsyn

External clock select bit

0 : XIN-XOUT

1 : XCIN-XCOUT

Processor mode bits

Nothing is arranged for this bit.

Fix this bit to “1”.

0 : Oscillating

1 : Stopped

Notes 1: This is not available in the flash memory version.

2: When (CPMA 7, 6) = (0, 0), the internal system clock can be selected between

f(XIN) and f(XIN)/2 by CCR7.

The internal clock

φ is the internal system clock divided by 2.

CPU mode register B

b7 b6 b5 b4 b3 b2 b1 b0

CPU mode register B

(CPMB : address 0116)

1 0

Name

Functions

At reset R W

Expanded data memory

access bit

HOLD function enable bit

b1b0

0 0 : No wait

0 1 : One-time wait

1 0 : Two-time wait

1 1 : Three-time wait

0 : EDMA output disabled

1 : EDMA output enabled

0 : HOLD function disabled

1 : HOLD function enabled

Slow memory wait select

bits

b3b2

0 0 : Software wait

0 1 : Not available

1 0 : RDY wait

1 1 : Software wait plus RDY input

anytime wait

Slow memory wait mode

select bits

Nothing is arranged for this bit.

Fix this bit to “0”.

Nothing is arranged for this bit.

Fix this bit to “1”.

Fig. 2.8.3 Structure of CPU mode register B

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