7643 datasheet(299/424 Pages) RENESAS

299 / 424 page

Rev.2.00

Aug 28, 2006

page 178 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.8 External device connection

(2) RDY wait

RDY wait is selected by setting “10” to the slow memory wait mode select bits (b3, b2 of CPMB).

When a fixed time of “L” (tsu) is input to the RDY pin at the beginning of a read/write cycle (before

φ cycle falls), the MCU goes to the RDY state. Then the read/write cycle can be extended by one

to three

φ cycles. The number of φ cycles to be extended can be selected by the slow memory

wait select bits (b1, b0 of CPMB).

Even if “L” is input to the RDY pin at the end of waited read/write cycle, the cycle is not extended.

When a fixed time of “H” (tsu) is input to the RDY pin at the beginning of a read/write cycle (before

φ cycle falls), the MCU is released from the RDY state.

Figure 2.8.5 shows the RDY wait timing example.

OUT

RDY

φOUT

ADOUT

DB IN/OUT

1 bus cycle

<< No Wait >>

Address

<< Wait >>

1 bus cycle

φOUT

ADOUT

DB IN/OUT

Address

tsu(RDY-

φ)

tsu(RDY-

φ)

Note: This example is the 1-cycle RDY wait .

Refer to Chapter 1 “Slow Memory Wait in PROCESSOR MODE” for 2- and

3-cycle RDY wait timings.

Fig. 2.8.5 RDY wait timing example

7643 Datasheet(PDF) 299 Page - Renesas Technology Corp