7643 datasheet(300/424 Pages) RENESAS

300 / 424 page

Rev.2.00

Aug 28, 2006

page 179 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.8 External device connection

(3) Software wait + Extended RDY wait

Extended RDY wait (software wait plus RDY input anytime wait) is selected by setting “11” to the

slow memory wait mode select bits (b3, b2 of CPMB). The read/write cycle can be extended when

a fixed time (tsu) of “L” is input to the RDY pin at the beginning of a read/write cycle (before

cycle falls). The RDY pin state is checked continually at each fall of

φ cycle until the RDY pin goes

to “H” and the cycle keeps being extended. When a fixed time of “H” (tsu) is input to the RDY pin

at the beginning of a read/write cycle (before

φ cycle falls), the MCU is released from the wait

within 1, 2, or 3

φ cycles as selected with the slow memory wait bits (b1, b0 of CPMB).

Figure 2.8.6 shows the extended RDY wait (software wait plus RDY input anytime wait) timing

example

Fig. 2.8.6 Extended RDY wait (software wait plus RDY input anytime wait) timing example

OUT

φOUT

ADOUT

DB IN/OUT

<< No Wait >>

Address

1 bus cycle

RDY

<< Wait >>

1 bus cycle

φOUT

ADOUT

DB IN/OUT

Address

tsu

1234

tsu

Note: This example is the 1-cycle extended RDY wait (RD).

The 1-cycle extended RDY wait (WR) is the same timing as this.

Refer to Chapter 1 “Slow Memory Wait in PROCESSOR MODE” for 2- and 3-cycle

extended RDY wait timings.

1. When a fixed time (tsu) of “L” is input to the RDY pin before

φ falls, the MCU goes to RDY state.

2. The RDY pin state is checked continually at each fall of

φ cycle.

3. The RDY pin is “L” at the

φ fall of the end of the current wait time, so that the read/write cycle is

extended for one wait once again.

4. When a fixed time (tsu) of “H” is input to the RDY pin before

φ falls, the RDY state is released after

the current wait time.

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