7643 datasheet(311/424 Pages) RENESAS

311 / 424 page

Rev.2.00

Aug 28, 2006

page 190 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.10 Clock generating circuit

2.10.2 Related registers

Fig. 2.10.2 Structure of CPU mode register A

Fig. 2.10.3 Structure of Clock control register

CPU mode register A

b7 b6 b5 b4 b3 b2 b1 b0

CPU mode register A

(CPMA : address 0016)

Name

Functions

At reset R W

Stack page select bit

Sub-clock (XCIN-XCOUT)

stop bit

Main clock (XIN-XOUT) stop

bit

b1b0

0 0 : Single-chip mode

0 1 : Memory expansion mode

1 0 : Microprocessor mode (Note 1)

1 1 : Not available

0 : Page 0

1 : Page 1

0 : Stopped

1 : Oscillating

Internal system clock

select bit (Note 2)

0 : External clock (XIN-XOUT or XCIN-XCOUT)

1 : fsyn

External clock select bit

0 : XIN-XOUT

1 : XCIN-XCOUT

Processor mode bits

Nothing is arranged for this bit.

Fix this bit to “1”.

0 : Oscillating

1 : Stopped

Notes 1: This is not available in the flash memory version.

2: When (CPMA 7, 6) = (0, 0), the internal system clock can be selected between

f(XIN) and f(XIN)/2 by CCR7.

The internal clock

φ is the internal system clock divided by 2.

Clock control register

b7 b6 b5 b4 b3 b2 b1 b0

Clock control register

(CCR : address 1F16)

Name

Functions

At reset R W

0 : XCOUT oscillation drive is enabled.

(When XCIN oscillation is enabled.)

1 : XCOUT oscillation drive is disabled.

XCOUT oscillation drive

disable bit (CCR5)

0 : XOUT oscillation drive is enabled.

(When XIN oscillation is enabled.)

1 : XOUT oscillation drive is disabled.

XOUT oscillation drive

disable bit (CCR6)

XIN divider select bit

(CCR7) (Note)

Note: This bit is valid when (b7, b6 of CPMA) = “00”.

0 : f(XIN)/2 is used for the system clock.

1 : f(XIN) is used for the system clock.

Nothing is arranged for these bits.

Fix these bits to “0”.

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