TMS320C6743CPTP2 datasheet(103/151 Pages) TI1

103 / 151 page

TMS320C6743

www.ti.com

SPRS565D – APRIL 2009 – REVISED JUNE 2014

Table 6-48. General Timing Requirements for SPI0 Slave Modes(1)

NO.

MIN

MAX

UNIT

tc(SPC)S

Cycle Time, SPI0_CLK, All Slave Modes

greater of 3P or 40

tw(SPCH)S

Pulse Width High, SPI0_CLK, All Slave Modes

tw(SPCL)S

Pulse Width Low, SPI0_CLK, All Slave Modes

Polarity = 0, Phase = 0,

to SPI0_CLK rising

Polarity = 0, Phase = 1,

Setup time, transmit data written to

to SPI0_CLK rising

tsu(SOMI_SPC)S

SPI before initial clock edge from

Polarity = 1, Phase = 0,

master.(2) (3)

to SPI0_CLK falling

Polarity = 1, Phase = 1,

to SPI0_CLK falling

Polarity = 0, Phase = 0,

18.5

from SPI0_CLK rising

Polarity = 0, Phase = 1,

18.5

Delay, subsequent bits valid on

from SPI0_CLK falling

td(SPC_SOMI)S

SPI0_SOMI after transmit edge of

Polarity = 1, Phase = 0,

SPI0_CLK

18.5

from SPI0_CLK falling

Polarity = 1, Phase = 1,

18.5

from SPI0_CLK rising

Polarity = 0, Phase = 0,

0.5tc(SPC)S -3

from SPI0_CLK falling

Polarity = 0, Phase = 1,

0.5tc(SPC)S -3

Output hold time, SPI0_SOMI valid

from SPI0_CLK rising

toh(SPC_SOMI)S

after

Polarity = 1, Phase = 0,

receive edge of SPI0_CLK

0.5tc(SPC)S -3

from SPI0_CLK rising

Polarity = 1, Phase = 1,

0.5tc(SPC)S -3

from SPI0_CLK falling

Polarity = 0, Phase = 0,

to SPI0_CLK falling

Polarity = 0, Phase = 1,

Input Setup Time, SPI0_SIMO valid

to SPI0_CLK rising

tsu(SIMO_SPC)S

before

Polarity = 1, Phase = 0,

receive edge of SPI0_CLK

to SPI0_CLK rising

Polarity = 1, Phase = 1,

to SPI0_CLK falling

Polarity = 0, Phase = 0,

from SPI0_CLK falling

Polarity = 0, Phase = 1,

Input Hold Time, SPI0_SIMO valid

from SPI0_CLK rising

tih(SPC_SIMO)S

after

Polarity = 1, Phase = 0,

receive edge of SPI0_CLK

from SPI0_CLK rising

Polarity = 1, Phase = 1,

from SPI0_CLK falling

(1)

P = SYSCLK2 period

(2)

First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on

SPI0_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI0_SIMO.

(3)

Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus

cycles must be accounted for to allow data to be written to the SPI module by the DSP CPU.

Peripheral Information and Electrical Specifications

103

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