TMS320C6743CPTP2 datasheet(105/151 Pages) TI1

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TMS320C6743

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SPRS565D – APRIL 2009 – REVISED JUNE 2014

Table 6-51. Additional(1) SPI0 Master Timings, 5-Pin Option(2) (3)

NO.

MIN

MAX

UNIT

Polarity = 0, Phase = 0,

0.5tc(SPC)M+ P + 5

from SPI0_CLK falling

Max delay for slave to

Polarity = 0, Phase = 1,

P + 5

deassert SPI0_ENA after final from SPI0_CLK falling

td(SPC_ENA)M

SPI0_CLK edge to ensure

Polarity = 1, Phase = 0,

master does not begin the

0.5tc(SPC)M+ P + 5

from SPI0_CLK rising

next transfer.(4)

Polarity = 1, Phase = 1,

P + 5

from SPI0_CLK rising

Polarity = 0, Phase = 0,

0.5tc(SPC)M+ P - 3

from SPI0_CLK falling

Polarity = 0, Phase = 1,

Delay from final SPI0_CLK

P - 3

from SPI0_CLK falling

edge to

td(SPC_SCS)M

master deasserting

Polarity = 1, Phase = 0,

0.5tc(SPC)M+ P - 3

SPI0_SCS (5) (6)

from SPI0_CLK rising

Polarity = 1, Phase = 1,

P - 3

from SPI0_CLK rising

Max delay for slave SPI to drive SPI0_ENA valid after

td(SCSL_ENAL)M

master asserts SPI0_SCS to delay the

C2TDELAY + P

master from beginning the next transfer,

Polarity = 0, Phase = 0,

2P - 5

to SPI0_CLK rising

Polarity = 0, Phase = 1,

0.5tc(SPC)M + 2P - 5

to SPI0_CLK rising

Delay from SPI0_SCS active

td(SCS_SPC)M

to first SPI0_CLK(7) (8) (9)

Polarity = 1, Phase = 0,

2P - 5

to SPI0_CLK falling

Polarity = 1, Phase = 1,

0.5tc(SPC)M + 2P - 5

to SPI0_CLK falling

Polarity = 0, Phase = 0,

3P + 3.6

to SPI0_CLK rising

Polarity = 0, Phase = 1,

0.5tc(SPC)M + 3P + 3.6

Delay from assertion of

to SPI0_CLK rising

td(ENA_SPC)M

SPI0_ENA low to first

Polarity = 1, Phase = 0,

SPI0_CLK edge.(10)

3P + 3.6

to SPI0_CLK falling

Polarity = 1, Phase = 1,

0.5tc(SPC)M + 3P + 3.6

to SPI0_CLK falling

(1)

These parameters are in addition to the general timings for SPI master modes (Table 6-48).

(2)

P = SYSCLK2 period

(3)

Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.

(4)

In the case where the master SPI is ready with new data before SPI0_ENA deassertion.

(5)

Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI0_SCS will remain

asserted.

(6)

This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].

(7)

If SPI0_ENA is asserted immediately such that the transmission is not delayed by SPI0_ENA.

(8)

In the case where the master SPI is ready with new data before SPI0_SCS assertion.

(9)

This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].

(10) If SPI0_ENA was initially deasserted high and SPI0_CLK is delayed.

Peripheral Information and Electrical Specifications

105

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