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MYX29GL01GS11DPIV2 Datasheet(PDF) 64 Page - Micross Components |
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MYX29GL01GS11DPIV2 Datasheet(HTML) 64 Page - Micross Components |
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64 / 68 page  MYX29GL01GS11DPIV2 Revision 1.0 - 01/26/2015 *Advanced information. Subject to change without notice. 64 1Gb GL-S MirrorBit® Eclipse™ Flash Memory MYX29GL01GS11DPIV2* Form #: CSI-D-685 Document 001 Figure 21: Back to Back (CE#) Write Operation Timing Diagram October 9, 2013 S29GL_128S_01GS_00_08 GL-S MirrorBit® Family 89 Data She e t 10.4.3 Alternate CE# Controlled Write Operations Note: 1. Not 100% tested. Figure 10.19 Back to Back (CE#) Write Operation Timing Diagram Table 10.9 Alternate CE# Controlled Write Operations Parameter Description VIO = 2.7V to VCC VIO = 1.65V to VCC Unit JEDEC Std tAVAV tWC Write Cycle Time (Note 1) Min 60 ns tAVWL tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE# Low during toggle bit polling Min 15 ns tWLAX tAH Address Hold Time Min 45 ns tAHT Address Hold Time From CE# or OE# High during toggle bit polling Min 0 ns tDVWH tDS Data Setup Time Min 30 ns tWHDX tDH Data Hold Time Min 0 ns tCEPH CE# High during toggle bit polling Min 20 ns t0EPH OE# High during toggle bit polling Min 20 ns tGHEK tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tELWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 25 ns tEHEL tCPH CE# Pulse Width High Min 20 ns Amax-A0 CE# OE# WE# DQ15-DQ0 tDS tDH tAS tAH tWC tCP tCPH tWS tWH Figure 22: (CE#) Write to Read Operation Timing Diagram 90 GL-S MirrorBit® Family S29GL_128S_01GS_00_08 October 9, 2013 D a t a S h e e t Figure 10.20 (CE#) Write to Read Operation Timing Diagram Amax-A0 CE# OE# WE# DQ15-DQ0 tACC tOE tCE tDF tOH tWC tAS tAH tDS tDH tWS tWH tOEH |
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