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MC68HC908AP16CFB Datasheet(PDF) 131 Page - Motorola, Inc |
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MC68HC908AP16CFB Datasheet(HTML) 131 Page - Motorola, Inc |
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131 / 440 page ![]() System Integration Module (SIM) SIM Bus Clock Control and Generation MC68HC908AP Family — Rev. 2.5 Data Sheet MOTOROLA 131 9.2 SIM Bus Clock Control and Generation The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 9-3. This clock can come from either an external oscillator or from the on-chip PLL. (See Section 8. Clock Generator Module (CGM).) Addr. Register Name Bit 7 654321 Bit 0 $FE00 SIM Break Status Register (SBSR) Read: RRRRRR SBSW R Write: NOTE Reset: 00000000 Note: Writing a logic 0 clears SBSW. $FE01 SIM Reset Status Register (SRSR) Read: POR PIN COP ILOP ILAD MODRST LVI 0 Write: POR: 10000000 $FE03 SIM Break Flag Control Register (SBFCR) Read: BCFE RRRRRRR Write: Reset: 0 $FE04 Interrupt Status Register 1 (INT1) Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0 Write: RRRRRRRR Reset: 00000000 $FE05 Interrupt Status Register 2 (INT2) Read: IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7 Write: RRRRRRRR Reset: 00000000 $FE06 Interrupt Status Register 3 (INT3) Read: 0 IF21 IF20 IF19 IF18 IF17 IF16 IF15 Write: RRRRRRRR Reset: 00000000 = Unimplemented Figure 9-2. SIM I/O Register Summary Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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