MC68HC908AP16CFB datasheet(136/440 Pages) MOTOROLA

136 / 440 page

System Integration Module (SIM)

Data Sheet

MC68HC908AP Family — Rev. 2.5

136

MOTOROLA

Figure 9-7. POR Recovery

9.3.2.2 Computer Operating Properly (COP) Reset

An input to the SIM is reserved for the COP reset signal. The overflow of

the COP counter causes an internal reset and sets the COP bit in the

SIM reset status register (SRSR). The SIM actively pulls down the RST

pin for all internal reset sources.

To prevent a COP module timeout, write any value to location $FFFF.

Writing to location $FFFF clears the COP counter and bits 12 through 5

of the SIM counter. The SIM counter output, which occurs at least every

213 – 24 ICLK cycles, drives the COP counter. The COP should be

serviced as soon as possible out of reset to guarantee the maximum

amount of time before the first timeout.

The COP module is disabled if the RST pin or the IRQ1 pin is held at

VTST while the MCU is in monitor mode. The COP module can be

disabled only through combinational logic conditioned with the high

voltage signal on the RST or the IRQ1 pin. This prevents the COP from

becoming disabled as a result of external noise. During a break state,

VTST on the RST pin disables the COP module.

PORRST

OSC1

ICLK

CGMOUT

RST

IAB

4096

CYCLES

$FFFE

$FFFF

IRST

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

MC68HC908AP16CFB Datasheet(PDF) 136 Page - Motorola, Inc