MC68HC908AP16CFB datasheet(201/440 Pages) MOTOROLA

201 / 440 page

Timer Interface Module (TIM)

I/O Registers

MC68HC908AP Family — Rev. 2.5

Data Sheet

MOTOROLA

201

When ELSxB:ELSxA = 0:0, this read/write bit selects the initial output

level of the TCHx pin. See Table 11-3. Reset clears the MSxA bit.

1 = Initial output level low

0 = Initial output level high

NOTE:

Before changing a channel function by writing to the MSxB or MSxA bit,

set the TSTOP and TRST bits in the TIM status and control register

(TSC).

ELSxB and ELSxA — Edge/Level Select Bits

When channel x is an input capture channel, these read/write bits

control the active edge-sensing logic on channel x.

When channel x is an output compare channel, ELSxB and ELSxA

control the channel x output behavior when an output compare

occurs.

When ELSxB and ELSxA are both clear, channel x is not connected

to an I/O port, and pin TCHx is available as a general-purpose I/O pin.

Table 11-3 shows how ELSxB and ELSxA work. Reset clears the

ELSxB and ELSxA bits.

Table 11-3. Mode, Edge, and Level Selection

MSxB:MSxA

ELSxB:ELSxA

Mode

Configuration

Output preset

Pin under port control;

initial output level high

Pin under port control;

initial output level low

Input capture

Capture on rising edge only

Capture on falling edge only

Capture on rising or

falling edge

Output

compare or

PWM

Toggle output on compare

Clear output on compare

Set output on compare

Buffered

output

compare or

buffered PWM

Toggle output on compare

Clear output on compare

Set output on compare

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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