MIMXRT8024DVL4A datasheet(18/103 Pages) NXP

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Table 3. Special signal considerations (continued)

Signal Name

Remarks

The crystal can be eliminated if an external 24 MHz oscillator is available in the system. In this case,

XTALO must be directly driven by the external oscillator and XTALI mounted with 18 pF capacitor.

The logic level of this forcing clock cannot exceed NVCC_PLL level.

If this clock is used as a reference for USB, then there are strict frequency tolerance and jitter

requirements. See OSC24M chapter and relevant interface specifications chapters for details.

GPANAIO

This signal is reserved for NXP manufacturing use only. This output must remain unconnected.

JTAG_

nnnn

The JTAG interface is summarized in Table 4. Use of external resistors is unnecessary. However,

if external resistors are used, the user must ensure that the on-chip pull-up/down configuration is

followed. For example, do not use an external pull down on an input that has on-chip pull-up.

JTAG_TDO is configured with a keeper circuit such that the non-connected condition is eliminated

if an external pull resistor is not present. An external pull resistor on JTAG_TDO is detrimental and

should be avoided.

JTAG_MOD is referenced as SJC_MOD in the i.MX RT1060X reference manual

(IMXRT1060XRM). Both names refer to the same signal. JTAG_MOD must be externally

connected to GND for normal operation. Termination to GND through an external pull-down

resistor (such as 1 kΩ) is allowed. JTAG_MOD set to hi configures the JTAG interface to mode

compliant with IEEE1149.1 standard. JTAG_MOD set to low configures the JTAG interface for

common SW debug adding all the system TAPs to the chain.

These signals are No Connect (NC) and should be disconnected by the user.

POR_B

This cold reset negative logic input resets all modules and logic in the IC.

May be used in addition to internally generated power on reset signal (logical AND, both internal

and external signals are considered active low).

ONOFF

ONOFF can be configured in debounce, off to on time, and max time-out configurations. The

debounce and off to on time configurations supports 0, 50, 100 and 500 ms. Debounce is used to

generate the power off interrupt. While in the ON state, if ONOFF button is pressed longer than

the debounce time, the power off interrupt is generated. Off to on time supports the time it takes to

request power on after a configured button press time has been reached. While in the OFF state,

if ONOFF button is pressed longer than the off to on time, the state will transition from OFF to ON.

Max time-out configuration supports 5, 10, 15 seconds and disable. Max time-out configuration

supports the time it takes to request power down after ONOFF button has been pressed for the

defined time.

TEST_MODE

TEST_MODE is for NXP factory use. The user can leave this signal floating or tie it to ground.

WAKEUP

A GPIO powered by SNVS domain power supply which can be configured as wakeup source in

SNVS mode.

NXP Semiconductors

Modules List

i.MX RT1060X Crossover Processors for Extended Products , Rev. 1, 06/2022

Data Sheet: Technical Data

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