MIMXRT8024DVL4A datasheet(26/103 Pages) NXP

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Table 13. USB PHY current consumption in power down mode

VDD_USB_CAP (3.0 V)

VDD_HIGH_CAP (2.5 V)

NVCC_PLL (1.1 V)

Current

5.1 μA

1.7 μA

< 0.5 μA

The currents on the VDD_HIGH_CAP and VDD_USB_CAP were identified to be the voltage divider circuits in the

USB-specific level shifters.

NOTE

4.2 System power and clocks

This section provide the information about the system power and clocks.

4.2.1 Power supplies requirements and restrictions

The system design must comply with power-up sequence, power-down sequence, and steady state guidelines as described in this

section to guarantee the reliable operation of the device. Any deviation from these sequences may result in the following situations:

• Excessive current during power-up phase

• Prevention of the device from booting

• Irreversible damage to the processor (worst-case scenario)

4.2.1.1 Power-up sequence

The below restrictions must be followed:

• VDD_SNVS_IN supply must be turned on before any other power supply or be connected (shorted) with

VDD_HIGH_IN supply.

• If a coin cell is used to power VDD_SNVS_IN, then ensure that it is connected before any other supply is switched on.

• An RC delay circuit is recommended for providing the delay between DCDC_IN stable and DCDC_PSWITCH. The total

RC delay should be 5-15 ms.

• DCDC_IN must reach a minimum 3.0 V within 0.3 x RC.

• Delay from DCDC_IN stable at 3.0 V min to DCDC_PSWITCH reaching 0.5 x DCDC_IN (1.5 V) must be at least 1 ms.

• Power up slew rate specification for other power domains is 360V/s – 36kV/s.

The POR_B input (if used) must be immediately asserted at power-up and remain asserted until after the last

power rail reaches its working voltage. In the absence of an external reset feeding the POR_B input, the internal

POR module takes control. See the

i.MX RT1060X Reference Manual (IMXRT106X0RM) for further details and to

ensure that all necessary requirements are being met.

NOTE

Need to ensure that there is no back voltage (leakage) from any supply on the board towards the 3.3 V supply (for

example, from the external components that use both the 1.8 V and 3.3 V supplies).

NOTE

USB_OTG1_VBUS, USB_OTG2_VBUS, and VDDA_ADC_3P3 are not part of the power supply sequence and may

be powered at any time.

NOTE

4.2.1.2 Power-down sequence

The following restrictions must be followed:

NXP Semiconductors

Electrical Characteristics

i.MX RT1060X Crossover Processors for Extended Products , Rev. 1, 06/2022

Data Sheet: Technical Data

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