MIMXRT8024DVL4A datasheet(73/103 Pages) NXP

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Table 63. HS200 interface timing specification (continued)

Parameter

Symbols

Min

Max

Unit

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)1

SD8

Card Output Data Window

tODW

0.5 x tCLK

—

1. HS200 is for 8 bits while SDR104 is for 4 bits.

4.9.3.5 Bus operation condition for 3.3 V and 1.8 V signaling

Signaling level of SD/eMMC4.3 and eMMC4.4/4.41 modes is 3.3 V. Signaling level of SDR104/SDR50 mode is 1.8 V. The DC

parameters for the NVCC_SD1 supply are identical to those shown in Table 22.

4.9.4 Ethernet controller (ENET) AC electrical specifications

The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints

for the physical interface.

4.9.4.1 ENET MII mode timing

This subsection describes MII receive, transmit, asynchronous inputs, and serial management signal timings.

4.9.4.1.1 MII receive signal timing (ENET_RX_DATA3,2,1,0, ENET_RX_EN, ENET_RX_ER, and

ENET_RX_CLK)

The receiver functions correctly up to an ENET_RX_CLK maximum frequency of 25 MHz + 1%. There is no minimum frequency

requirement. Additionally, the processor clock frequency must exceed twice the ENET_RX_CLK frequency.

Figure 47 shows MII receive signal timings. Table 64 describes the timing parameters (M1–M4) shown in the figure.

ENET_RX_CLK (input)

ENET_RX_DATA3,2,1,0

ENET_RX_ER

ENET_RX_EN

(inputs)

Figure 47. MII receive signal timing diagram

Table 64. MII receive signal timing

Characteristic1

Min.

Max.

Unit

ENET_RX_DATA3,2,1,0, ENET_RX_EN, ENET_RX_ER to

ENET_RX_CLK setup

—

ENET_RX_CLK to ENET_RX_DATA3,2,1,0, ENET_RX_EN,

ENET_RX_ER hold

—

ENET_RX_CLK pulse width high

35%

65%

ENET_RX_CLK period

ENET_RX_CLK pulse width low

35%

65%

ENET_RX_CLK period

NXP Semiconductors

Electrical Characteristics

i.MX RT1060X Crossover Processors for Extended Products , Rev. 1, 06/2022

Data Sheet: Technical Data

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