MIMXRT8024DVL4A datasheet(52/103 Pages) NXP

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CSI_PIXCLK

CSI_VSYNC

CSI_DATA[23:00]

CSI_HSYNC

Figure 28. CSI Gated clock mode—sensor data at rising edge, latch data at falling edge

Table 47. CSI gated clock mode timing parameters

Parameter

Symbol

Min.

Max.

Units

CSI_VSYNC to CSI_HSYNC time

tV2H

33.5

—

CSI_HSYNC setup time

tHsu

—

CSI DATA setup time

tDsu

—

CSI DATA hold time

tDh

—

CSI pixel clock high time

tCLKh

3.75

—

CSI pixel clock low time

tCLKl

3.75

—

CSI pixel clock frequency

fCLK

—

MHz

4.6.1.2 Ungated clock mode timing

Figure 29 shows the ungated clock mode timings of CSI, and Table 48 describes the timing parameters (P1–P6) that are shown

in the figure. In ungated mode the CSI_VSYNC and CSI_PIXCLK signals are used, and the CSI_HSYNC signal is ignored.

CSI_PIXCLK

CSI_VSYNC

CSI_DATA[23:00]

Figure 29. CSI ungated clock mode—sensor data at falling edge, latch data at rising edge

NXP Semiconductors

Electrical Characteristics

i.MX RT1060X Crossover Processors for Extended Products , Rev. 1, 06/2022

Data Sheet: Technical Data

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