MIMXRT8024DVL4A datasheet(46/103 Pages) NXP

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Table 38. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X1 (continued)

Symbol

Parameter

Min

Max

Unit

TIS

Setup time for incoming data

—

TIH

Hold time for incoming data

—

TIS

TIH

SCK

SIO[0:7]

TIS

TIH

Internal Sample Clock

Figure 19. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X0, 0X1

Timing shown is based on the memory generating read data on the SCK falling edge, and FlexSPI controller

sampling read data on the falling edge.

NOTE

4.5.2.1.2 SDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x3

There are two cases when the memory provides both read data and the read strobe in SDR mode:

• A1—Memory generates both read data and read strobe on SCK rising edge (or falling edge)

• A2—Memory generates read data on SCK falling edge and generates read strobe on SCK rising edgeSCK rising edge

Table 39. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case A1)

Symbol

Parameter

Value

Unit

Min

Max

Frequency of operation

—

166

MHz

TSCKD

Time from SCK to data valid

—

TSCKDQS

Time from SCK to DQS

—

TSCKD - TSCKDQS

Time delta between TSCKD and TSCKDQS

-2

NXP Semiconductors

Electrical Characteristics

i.MX RT1060X Crossover Processors for Extended Products , Rev. 1, 06/2022

Data Sheet: Technical Data

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