MIMXRT8024DVL4A datasheet(57/103 Pages) NXP

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Table 52. SPDIF timing parameters (continued)

Characteristics

Symbol

Timing Parameter Range

Unit

Min

Max

Modulating Tx clock (SPDIF_ST_CLK) period

stclkp

40.0

—

SPDIF_ST_CLK high period

stclkph

16.0

—

SPDIF_ST_CLK low period

stclkpl

16.0

—

SPDIF_SR_CLK

(Output)

srckp

srckph

srckpl

Figure 33. SPDIF_SR_CLK timing diagram

SPDIF_ST_CLK

(Input)

stclkp

stclkph

stclkpl

Figure 34. SPDIF_ST_CLK timing diagram

4.8 Analog

The following sections provide information about analog interfaces.

4.8.1 DCDC

Table 53 introduces the DCDC electrical specifications.

Table 53. DCDC electrical specifications

Mode

Buck mode, one output

Notes

Input voltage

3.3 V

Min = 2.8 V, Max = 3.6 V

Output voltage

1.1 V

Configurable 0.8 - 1.575 with 25 mV one step

in Run mode

Max loading

500 mA

—

Loading in low power modes

200 μA ~ 30 mA

—

Efficiency

90% max

@150 mA

Low power mode

Open loop mode

Ripple is about 15 mV in Run mode

Run mode

• Always continuous mode

Configurable by register

Table continues on the next page...

NXP Semiconductors

Electrical Characteristics

i.MX RT1060X Crossover Processors for Extended Products , Rev. 1, 06/2022

Data Sheet: Technical Data

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