MIMXRT8024DVL4A datasheet(43/103 Pages) NXP

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4. WE# low time is configurable by SEMC_*CR0.WEL. WEL field setting value is 0x0 in above table. When WEL is set with value

N, TWEL min time should be ((N + 1) x TCK - 1). See the i.MX RT1060X Reference Manual (IMXRT1060XRM) for more detail

about SEMC_*CR0.WEL register field.

Figure 15 shows the output timing in ASYNC mode.

Internal clock

ADDR

ADV#

TAVO

TAHO

DATA

WE#

TCK

TDVO

TDHO

Figure 15. SEMC output timing in ASYNC mode

4.5.1.1.2 SEMC output timing in SYNC mode

Table 33 shows SEMC output timing in SYNC mode.

Table 33. SEMC output timing in SYNC mode

Symbol

Parameter

Min.

Max.

Unit

Comment

Frequency of operation

—

166

MHz

—

TCK

Internal clock period

—

TDVO

Data output valid time

—

These timing parameters

apply to Address/Data/DM/CKE/

control signals with SEMC_CLK

for SDRAM.

TDHO

Data output hold time

-1

—

Figure 16 shows the output timing in SYNC mode.

SEMC_CLK

DATA

TDHO

TDVO

Figure 16. SEMC output timing in SYNC mode

NXP Semiconductors

Electrical Characteristics

i.MX RT1060X Crossover Processors for Extended Products , Rev. 1, 06/2022

Data Sheet: Technical Data

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